This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ia7c95879b7c96f8ed0913959f587f7deefe62dec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 12eca76469
Original-Change-Id: I2a789cff40fb0e6bd6d84565531d847afb3f8bed
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19780
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514187
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I269ad36b81a4365807d036038d16de2d5077f253
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2cd03f1696
Original-Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19779
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514186
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ib2484bdf3e8a45eefc46c71ae4c52fb7d07ff6bb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2d9a99535d
Original-Change-Id: Id3f05a2ea6eb5e31ca607861973d96b507208115
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19778
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514185
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I76ceda11937839f758cd7c2b48f9164c5ee5d109
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f8662ca3bc
Original-Change-Id: Ic937cbf93b87f5e43f7d70140b47fa97bcd7757e
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19777
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514184
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ie955c903e299be8ff49e73b68c16b37ff833188c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e424a59729
Original-Change-Id: I6cc8c339e008e16449fa143c1d21e23534bdaf0b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19776
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514183
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I4a3b46bd16c8f384e76a38817fce86318c5be516
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 56c88ebc02
Original-Change-Id: I48b242dd6226e392ed0f403051843b3ae02cd9a4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19773
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/514182
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I8d8cf520a53cd74d50ce658aacd0cb59ac8f0438
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e173ee8f01
Original-Change-Id: Ie4ec74fccaf25900537ccd5c146bb0a333a2754c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19772
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513961
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: Ief26dec8c156ce1fbc87cab0f3504c091d7c048c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 23d5d99098
Original-Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19771
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513960
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I5cce241a0726571f522f69d3bfec7c18d621e6e3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 02c0743a24
Original-Change-Id: Ib0d6e4e8185ce1285b671af5ebcead1d42e049bc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19770
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513959
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I1d10c535ad7d5bb8545e9ad463b9938ed2cff4f1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b46e9f6029
Original-Change-Id: I873b96d286655a814554bfd89f899ee87302b06d
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19769
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513958
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The SoC code was never completed. It's just a skeleton that gets
in the way of refactoring other code. Likewise, the mainboard was
never completed either. Just remove them both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I19d42549463e9726bcd4bcd119634733a933e184
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 250715eb2f
Original-Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19823
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/513957
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add support to the Intel common firmware Kconfig and Makefile.inc to
allow the embedded controller (EC) blob to be added to the final
binary through ifdtool.
TEST=Add ec.bin and enable in config, build is successful.
Change-Id: Ic4cc8d05f5cc6a303fe33807cf99c3081ac87dba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0fb6568444
Original-Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19719
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513956
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Field Programmable Fuses (FPF) status maintained by
CSME in bits 30:31 of FWSTS6 for Skylake and Kabylake.
FPF committed means CSME has blown the fuses.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3db6962e0e70038430c774b781cb55b3d069973f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4a907c79a2
Original-Change-Id: If63c7874e6c894749df8100426faca0ad432384b
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19747
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/513955
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia9167fc82c36d2e1ae2a681418dea2d91a544c78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f714965e8d
Original-Change-Id: I08dd7a8c0d42d4ec7c6ff65a82553fe1efbcc424
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/513954
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add GLK PCI IDs for I2C to use common I2C code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I594ddafbab9ee64f5cb2f8e7732784ea466a0d19
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3038e9bd08
Original-Change-Id: I2144199345e6382984c367f6a77f0cbb0a93daea
Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19782
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513953
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ic052854ef87fc88d4c25b6d14b8deb4fafe1f0fc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7941c96f8e
Original-Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19798
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513951
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is useful for debugging based on eventlog to identify if platform
entered normal or deep Sx.
BUG=b:38436041
Change-Id: Id63cf4d97126770e2a32a508d10ae5aff0d3e32b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 75ef6ec29e
Original-Change-Id: Ic7d8e5b8aafc07aed385fe3c4831ab7d29e1f890
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19797
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513950
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use SATA common code from soc/intel/common/block/sata
and clean up code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I26f5ca6de3d9cbaa09faac09bbc86ecf3402cde3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fd8e00092a
Original-Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19735
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510781
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add SATA code support in intel/common/block to initilalize
SATA controller, allocate resources and configure SATA port
status.
BUG=none
BRANCH=none
TEST=none
Change-Id: I53190966c44685573e636375444b471a6dec0f22
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1b1ecae0a4
Original-Change-Id: I42ec0059f7e311a232c38fef6a2e050a3e2c0ad3
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19734
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510780
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifccff937795c9b1f710c527c0d3816b3e4731486
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2d689f9e0d
Original-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19665
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510778
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I72a8270841ec229a2e27be71f3a6b3262640e6f1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4bbfe57959
Original-Change-Id: I6e710b95cade0ea68f787f33c0070613d64b6da6
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19743
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/510777
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I781280dad7477dd55788db2e487e20f4ec911b33
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10326ba889
Original-Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19801
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510773
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove guards and let the linker take care of it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I88864bb4de1b4185efb8ea8d42c61882dda1caf5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bb72852baf
Original-Change-Id: I96ad8002845082816153ca5762543768998a5619
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19744
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/510772
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9ed31c150e8a3e3371f91027c62a76530b7dc99b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 27f0ca18bc
Original-Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19767
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510771
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
All those boards do not have a serial port.
Don't attempt to decode the COMA/COMB IO range.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14fd3107b5fcf74c04d319b71971058e4f39736c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 93eac6a89d
Original-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19571
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510770
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibed8577d19b6490545019d6bf142230c82fb181c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ac27d3688a
Original-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19570
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510768
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a830468bbd1ddc8f0b815836234d9c0de019b5b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7565cf1a49
Original-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19543
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510767
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Hides JEDEC steps using the RAM_SPEW macro.
Also hides a hexdump of SPDs.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9367a693d565076be2740948a892d0aa3bbdba1a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cfa2eaa4cc
Original-Change-Id: Ie2b484cf1f1d296823df0473e852d9d07ca20246
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18924
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/510766
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ec6e0dbb1006be79b9a9412d5a60eb1c4b4590d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3db82be764
Original-Change-Id: I77aabf98ea48c6e8bdbe322f89666935f59a289a
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19760
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/510765
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This improves readability.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib654ffde2e45c442895b1d703b2e206ec063838d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: abc504f427
Original-Change-Id: Ib4387a4f4092053dab273191a73edb0ef31a79f6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19691
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/510764
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
It is not really known why there is such a long delay, but it works
fine without it.
TESTED on ga-g41m-es2l.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7401ed84900a513ba2240e0c3b823aa46b5f7ec2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e729366d7a
Original-Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19514
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/510763
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b89a0b86082e5b57a53c5c7c6fd9fe0c9db6167
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1222162d12
Original-Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/510762
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Only board using this code was tyan s2735 which was removed in
f76de841f1 "[REMOVAL] tyan/s2735"
BUG=none
BRANCH=none
TEST=none
Change-Id: I75d2a72adf24ed89d74631f4101ab8b74c26f198
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bd23bd62b4
Original-Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19507
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/509527
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=b:37712455
Change-Id: Ia5aa6665db0f8199de8d2cf363272d7e2b676363
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 365d97e938
Original-Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19766
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509526
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix SPD as per the vendor-provided data.
BUG=b:37712790
Change-Id: Id2054c54ec61c7bd3e9161c70506f45d31fd36d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 77be7339cd
Original-Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19749
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509525
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I29deaa94b0339972aa016b77a80344da6abadd06
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e2fc5e25f2
Original-Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19757
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509524
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I996ff78f75296cc5bc38b6e760545b9b7dd810c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a1491574ef
Original-Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19708
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509523
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I817a51fc7b480f6532941fccd08a6179dbc14378
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bd9e32efdd
Original-Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19707
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509522
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove unused function declaration spi_fram_probe_ramtron.
BUG=b:38330715
Change-Id: I05900361e86178b297c29f57d7e907a237cf3452
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7863395ad1
Original-Change-Id: I05e6c5c2b97d6c8a726c0e443ad855f9bcb703f9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19706
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/509521
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: Iea541abe70577dc357e8de4f62b5cd4b75c889e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 30221b45e0
Original-Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19705
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509520
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I1643c17f10226e943a3f94d4619f7e87f4b6777c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fc1a123aa7
Original-Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19704
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509519
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Instead of storing spi flash device structure in spi flash driver, use
boot_device_spi_flash callback to obtain pointer to boot device spi
flash structure.
BUG=b:38330715
Change-Id: I83a384ce1b417869167d9dbeb38ed7a9900f0e11
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f422fd2c78
Original-Change-Id: Idd50b7644d1a4be8b62d38cc9239feae2215103c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19703
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/509518
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This allows callers to retrieve handle to the boot device spi_flash structure.
BUG=b:38330715
Change-Id: Ica5e952ccca4f73dc35bfba31e4f9e0d880f0390
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 78bc6ddfd0
Original-Change-Id: I1c07327115e0449cbd84d163218da76a6fa2cea0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19726
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/509517
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested and working:
* HDD LED
* Booting GNU Linux 4.9 from HDD using SeaBios
* Booting GNU Linux 4.9 from USB using SeaBios
* Native GFX init
* All Fn function keys
* Speakers
* PCIe Wifi
* Camera
* WWAN
* Fan (Dynamic Thermal Managment)
* Flashing using internal programmer
* Dual memory DIMMs running at up to DDR3-1866
* AC events
* Touchpad, trackball and keyboard
* USB3 ports running at SuperSpeed
* Ethernet
* Headphone jack
* Speaker mute
* Microphone mute
* Volume keys
* Fingerprint sensor
* Lid switch
* Thinklight
* TPM (disable SeaBios CONFIG_TCGBIOS)
* CMOS options:
** power_on_after_fail
** reboot_counter
** boot_option
** gfx_uma_size
** usb_always_on
Untested:
* Booting Windows
* Hybrid graphics
* Docking station
* VGA
Broken:
* Wifi LED is always on
BUG=none
BRANCH=none
TEST=none
Change-Id: I8e9aa289a838691ce6edcddeb42cb4d1a865a609
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 714baa119b
Original-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18011
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/509516
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
