mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
UPSTREAM: soc/baytrail: fix ACPI table by recollecting TOLM
Adapted from Chromium commit 8fbe1e7 for soc/braswell
(also review.coreboot.org/#/c/20060/); same issue affects
baytrail as well.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
BUG=none
BRANCH=none
TEST=none
Change-Id: I87cc97e3d8270801b6924b310919ad7293f17626
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f05d2e17b0
Original-Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20081
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531200
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
parent
2fbafff002
commit
43f407c789
1 changed files with 9 additions and 2 deletions
|
@ -20,7 +20,7 @@
|
|||
#include <device/pci_ids.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
#include <arch/acpi.h>
|
||||
|
||||
#include <stddef.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/iosf.h>
|
||||
#include <soc/pci_devs.h>
|
||||
|
@ -65,7 +65,14 @@
|
|||
|
||||
uint32_t nc_read_top_of_low_memory(void)
|
||||
{
|
||||
return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
|
||||
MAYBE_STATIC uint32_t tolm = 0;
|
||||
|
||||
if (tolm)
|
||||
return tolm;
|
||||
|
||||
tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
|
||||
|
||||
return tolm;
|
||||
}
|
||||
|
||||
static void nc_read_resources(device_t dev)
|
||||
|
|
Loading…
Add table
Reference in a new issue