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Youness Alaoui 0f8df16b57 UPSTREAM: pciexp_device: Remove useless write on a read-only register
The Role-Based Error Reporting is not a configurable field,
it's a read only field in the Device Capability register.
This code was old and comes from commit f6eb88ad but evidently
is not useful in any way. The PCIe Specification [1] states
that it's read-only and must always be set to 1.

I have also done tests on purism/librem13 hardware, trying to
change that value, without any success.

[1]: PCI Express Base Specification Revision 3.0
     Page 612

BUG=none
BRANCH=none
TEST=none

Change-Id: Id4dff17957fbd6e1f54ab0917d4f9c7b557149d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2f48b7b1e9
Original-Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19901
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531684
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-06-12 14:16:00 -07:00
configs UPSTREAM: configs/builder: Remove pre-defined VGA bios file 2017-01-22 05:03:18 -08:00
Documentation UPSTREAM: Use more secure HTTPS URLs for coreboot sites 2017-06-12 08:47:49 -07:00
payloads UPSTREAM: payloads/Kconfig: Add NO_DEFAULT_PAYLOAD 2017-06-12 08:47:51 -07:00
src UPSTREAM: pciexp_device: Remove useless write on a read-only register 2017-06-12 14:16:00 -07:00
util UPSTREAM: msrtool: Remove no-pic from CFLAGS 2017-06-12 14:15:55 -07:00
.checkpatch.conf Drop --exclude statement from .checkpatch.conf 2017-03-13 17:53:59 -07:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore UPSTREAM: .gitignore: ignore blobtool binary 2017-05-15 08:17:54 -07:00
.gitmodules Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COMMIT-QUEUE.ini DO NOT UPSTREAM: COMMIT-QUEUE: Add strago to the pre-CQ 2017-06-01 16:50:56 -07:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc UPSTREAM: gnat.adc: Do not generate assertion code for Refined_Post 2016-11-03 14:44:05 -07:00
MAINTAINERS UPSTREAM: Use www.coreboot.org over coreboot.org 2017-06-12 08:47:49 -07:00
Makefile UPSTREAM: Makefile: add 'filelist' target 2017-06-12 08:47:54 -07:00
Makefile.inc UPSTREAM: Use more secure HTTPS URLs for coreboot sites 2017-06-12 08:47:49 -07:00
PRESUBMIT.cfg Make upstream tree CrOS SDK friendly 2016-05-12 15:42:17 -06:00
README UPSTREAM: Use more secure HTTPS URLs for coreboot sites 2017-06-12 08:47:49 -07:00
toolchain.inc UPSTREAM: Remove libverstage as separate library and source file class 2017-03-29 13:43:09 -07:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.