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UPSTREAM: soc/skylake: add ACPI method to generate USB port info

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Add ACPI method GPLD to generate port location data when
passed visiblity info.  Will be used by _PLD method in
board-specific USB .asl files.

BUG=none
BRANCH=none
TEST=none

Change-Id: I9f566b4c7117981e58709d3b8b52b410a5e3bbaf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dc1b78130a
Original-Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19975
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531191
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Matt DeVillier 2017-04-22 16:36:10 -05:00 • committed by chrome-bot
parent f846ba1a40
commit c474c17524
1 changed files with 20 additions and 0 deletions
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20
src/soc/intel/skylake/acpi/xhci.asl
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@ -223,6 +223,26 @@ Device (XHCI)
{
Name (_ADR, Zero)
// GPLD: Generate Port Location Data (PLD)
Method (GPLD, 1, Serialized)
{
Name (PCKG, Package (0x01)
{
Buffer (0x10) {}
})
// REV: Revision 0x02 for ACPI 5.0
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
Store (0x02, REV)
// VISI: Port visibility to user per port
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
Store (Arg0, VISI)
Return (PCKG)
}
/* USB2 */
Device (HS01) { Name (_ADR, 1) }
Device (HS02) { Name (_ADR, 2) }