- remove old, buggy NGI code from falco/peppy variants
- remove superfluous INTEL_DP/INTEL_DDI configs, since already
selected by northbridge/haswell
- always use libgfxinit when use native init config selected
- enable NGI/libgfxinit for all slippy variants
The reset of the old Haswell NGI code will be cleaned up in
a subsequent patchset.
Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init
using SeaBIOS and Tianocore payloads on peppy, wolf variants
[pg: add CQ-DEPEND to cover all pending graphics commits.
There are some fun little bugs and fixes along the chain.]
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:538580
Change-Id: Ie127751e69309b2f3082e96ec1689c2600f4e526
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 472d5111ad
Original-Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18824
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/533038
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As the hardware designed on gru, the AP_I2C_TP_PU_EN (gpio3_b4) controlled
the SCL/SDA status to avoid leakage. And the gpio3_b4 of rk3399 pull
resistor is 26k~71k and 3.3v for supply power, and gpio3_b4 pin connected
2.2k resistor to i2c of TP device.
The default of this gpio status is pulled up during the start to bootup,
it's very weak drive for the TP device that maybe cause to trigger the
recovery process of elan's firmware.
Also, the Elan updated its firmware(102.0.5.0) to delay checking the
i2c of touchpad is greater than 1 second.
So we have to drive the stronger pull-up within 1 second of powering up
the touchpad to prevent its firmware from falling into recovery.
BUG=b:36705749
BRANCH=gru
TEST=none
Old-change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibb0ba3eff09de727e60a2bff5603deade4dc3d54
Reviewed-on: https://chromium-review.googlesource.com/537772
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
I had a stupid. :( Asterisks have a special meaning in regexes, but I
just wanted to match three literal ones. This kills the regex parser.
BUG=chromium:729621
Change-Id: Ia6149e72715d651c914583ed3235680ce5b7a2e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20171
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/537138
Ensure that the provided ME/TXE firmware is valid, using the
check capabilities of me_cleaner.
me_cleaner checks that the fundamental partition is available and
it has a correct signature. The checks performed by me_cleaner
aren't exhaustive, but they should find at least whether the user
has provided an empty or corrupted firmware.
me_cleaner has been tested on all the ME (6-11.6) and TXE (1-3)
firmwares available here [1], and it hasn't reported any false
positive.
[1] http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:535697
Change-Id: Idcda139803b2d64813ece6cfbadac5ef0997483e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 16719ad143
Original-Change-Id: Ie6ea3b4e637dca4097b9377bd0507e84c4e8f687
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18768
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/533094
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Separate the required CPPFLAGS from environment overridable CFLAGS.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id32f44086ede9f8058cfa57a09a9bbd98da6c4e4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cce508fed2
Original-Change-Id: I0c1c0a1cebc7f7971634bf57d4a2370939c43fda
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/20175
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/535635
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I120c3e5823abb08ce8b636306b54ac76848a5f77
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cde2bdf496
Original-Change-Id: Ib4fc326c6612f2d142c8a5220949fbb4b97c37a1
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/20176
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/535636
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:535635
Change-Id: I51b34fa7492d0b60d7f06d8789b40e877170fcfe
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: af83db2659
Original-Change-Id: I66a243486a347313103ffd2cb2ca0447228e4054
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19586
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/533095
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
I'm pretty much already doing this anyway, so I might as well document
it. Separating out some older ARM SoCs that were added by other people
and are pretty much orphaned now.
I can also fill out the MISSING: MEMLAYOUT point (since I wrote that).
[pg: add tons of trailers in the commit message
to make gerrit-rebase sane again]
BUG=none
BRANCH=none
TEST=none
Change-Id: I927661db7be11ef7d58e18028ab62d9caf2f353e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c34e41fef6
Original-Change-Id: I8b78d592a1ed68a42e5785ebdc13df2edf9007bf
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20137
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Gerrit-Rebase-Ignore-CLs-Before: https://review.coreboot.org/18141
Ignore-CL-Reviewed-on: https://review.coreboot.org/18954
Ignore-CL-Reviewed-on: https://review.coreboot.org/18955
Ignore-CL-Reviewed-on: https://review.coreboot.org/18988
Ignore-CL-Reviewed-on: https://review.coreboot.org/19279
Ignore-CL-Reviewed-on: https://review.coreboot.org/19356
Ignore-CL-Reviewed-on: https://review.coreboot.org/19430
Ignore-CL-Reviewed-on: https://review.coreboot.org/19476
Ignore-CL-Reviewed-on: https://review.coreboot.org/19596
Ignore-CL-Reviewed-on: https://review.coreboot.org/20090
Ignore-CL-Reviewed-on: https://review.coreboot.org/20091
Reviewed-on: https://chromium-review.googlesource.com/533037
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideb937d7f7bde4ac4203b3f9686cdedab43c446c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 049347fee0
Original-Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19678
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/531732
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
BUG=none
BRANCH=none
TEST=none
Change-Id: I63ba605ab32523bb9632d530c7e938e7083be7d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9ed74b54b5
Original-Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19717
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/531731
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1a51fa7a94196e5dbb396e8baddf41f5f05b3f0a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dcd3cef874
Original-Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19716
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/531730
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix line over 80 characters, spaces required around comparisons,space
required after close brace '}', comma ',', semicolon ';', space
prohibited after ')' errors and warnings
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibdfc8053dcc260e7ded7f528aaf7c7bf15333893
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f6934f5c6c
Original-Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e
Original-Signed-off-by: Evelyn Huang <evhuang@google.com>
Original-Reviewed-on: https://review.coreboot.org/20099
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531729
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O.
Tested, working:
* Booting Linux 4.11.3 and Windows 8.1 from USB and HDD
* Resume from S3 (Linux and Windows)
* Native raminit (DDR2-800)
* Native graphics init (SeaBIOS, Linux)
* Graphics init with VGA BIOS (SeaBIOS, Windows)
* PCI-E x16 PEG slot, PCI-E x1 slot from southbridge
* Realtek ALC888 HD Audio (including front panel and jack detection)
* Realtek R8168 Gigabit LAN
* Both SATA ports
* USB 1.1 and 2.0 devices (keyboard, mass storage)
* PC speaker beep
* COM header
* Super I/O Environment controller (temps, voltage, fans)
* PS/2 keyboard and mouse
* Flashing with `flashrom -p internal`
* 1MiB and 2MiB SPI flash chips
* CMOS gfx_uma_size
Appears, OS driver loads, but otherwise untested:
* IrDA header
* CIR header
* TPM header
Untested:
* S/PDIF digital audio
Tested, known broken:
* CMOS power_on_after_fail
* USB keyboard in secondary payloads
BUG=none
BRANCH=none
TEST=none
Change-Id: Iecb5ecf8a718755b5ce8f1ea52a803f609fea726
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 82651463e3
Original-Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20027
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531728
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Test: boot OS (Ubuntu, Windows 10) on librem13v2, verify BT
function key toggle now works correctly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I263e72ba44dee7428d2b46533a6bff66475213eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab7127771d
Original-Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19897
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531727
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
I updated my spike patch[1] to cleanly apply to current spike master.
As a side effect, the UART is now at 0x02100000.
[1]: https://github.com/riscv/riscv-isa-sim/pull/53
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibc0fdb395099e54c8aec2d37b28c2c4489500b08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 035cf71822
Original-Change-Id: I4cb09014619e230011486fa57636abe183baa4be
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/20126
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/531726
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix line over 80 characters, unnecessary braces for single statement
blocks, spaces before close parantheses errors and warnings.
Signed-off-by: Evelyn Huang <evhuang@google.com>
BUG=none
BRANCH=none
TEST=none
Change-Id: I1d4319f7dda4d94d867d995ad89e9995ecc9c67b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ccc5513bd7
Original-Change-Id: I31b1932a2c1e401e56751e0c790bcc6287fb550d
Original-Reviewed-on: https://review.coreboot.org/20097
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531725
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix space prohibited between function name and open parenthesis, line
over 80 characters, unnecessary braces for single statement blocks,
space required before open brace errors and warnings
BUG=none
BRANCH=none
TEST=none
Change-Id: Id624639572ab0f643a35f47aceba0c4ecbdc8249
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 877b586691
Original-Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95
Original-Signed-off-by: Evelyn Huang <evhuang@google.com>
Original-Reviewed-on: https://review.coreboot.org/20096
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531724
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c6088dfff54afb4090490d890caacc445bd5067
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 53de6cd1c3
Original-Change-Id: I5a674cd7a360a0dd040c859ec1f8d760d7c83364
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20130
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531723
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I21585cc31b8534a517474ae09368841235c26f2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a3d0bfc1f
Original-Change-Id: Id88455f2c7c28e0b298675b9af2a39361759a34a
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19120
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531722
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I1dd7c26c911c13e4ab09e688c7b191bf7dd169d5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e20f3d02b5
Original-Change-Id: I1c4b30ab47e12ec35cb681ec5c6635ecd20aa2e5
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/19121
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531721
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for google/rambi
as to not break compilation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3afebbfaf56aa8cc9756d8878f9dda458d81f679
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e34a7705e6
Original-Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531720
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Unfortunately, some external websites and projects are spelling coreboot
with an uppercase C, so references to those pages can't be changed
without breaking the link.
BUG=none
BRANCH=none
TEST=none
Change-Id: I577e92745dcb9a85b09b6ac77f247801b4b37086
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 4b18a922f0
Original-Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20031
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531719
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This device is extremely similar to the IT8718F, so support is based on
existing support for the IT8718F. The CIR device is only detected by
Linux/Windows from the ACPI tables, so ACPI support is extended from the
IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K.
Tested, working:
* Serial port 1
* Environment controller
- Temperature monitoring
- Voltage monitoring
- Fan control (automatic and manual)
* PS/2 keyboard and mouse
Appears, OS driver loads, but otherwise untested:
* Serial port 2
* Consumer IR
Untested:
* Floppy controller
* Parallel port
* GPIO
BUG=none
BRANCH=none
TEST=none
Change-Id: I4abe90a500a674e5bf543338a400803efd205b96
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1318ea600b
Original-Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20026
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/531718
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I361efbbe6d514726e2c48700fcefd8a4aaa10d5c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: da8ca6561f
Original-Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20025
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/531717
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: Idaefecddbf949525e2a26ca703257467bb24558e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 901bdb3795
Original-Change-Id: Id4a079d868c5c806c769b5559833566e8a6a8a71
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20077
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/531716
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Some Super I/O PnP devices are detected by string matching the hardware
ID. Allow providing a custom HID to override the default generic one.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ide39011430f1fade78505492cbffabc08e3e7618
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d2a86da6e6
Original-Change-Id: I7793b7d53c9d94667675f9dee63358521ac8c4be
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20076
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/531715
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Some Super I/O logical devices have three I/O port ranges, such as the
GPIO on the IT8720F. Allow specifying a third I/O range. While here, fix
a typo in the I/O range description.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6dc205501ab40d8c57cbef0ce35653ddd7d6ac7b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: eeef6459a3
Original-Change-Id: Idad03f3881e0fbf2135562316d177972f931afec
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20024
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/531714
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=b:37088992
Change-Id: Iee15566aefaa9cbddcdaaec690fa24011f247d4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0f1dc0ef74
Original-Change-Id: If0b495234d6e498d5c64ba4dd186440cd7a1c5c6
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20121
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531713
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an
input), SMBus SPD addresses are accepted from the mainboard and not
calculated within the spd_bin library routines. Use the addr_map
values to print correct address in dump_spd_info.
BUG=none
BRANCH=none
TEST=none
Change-Id: I90ce930c23cd49ff93e4d5c8067810ee77598b86
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a26f9da6ba
Original-Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20118
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Shelley Chen <shchen@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531712
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch makes SOC files to use common/block/cpu/cpulib.c
file's helper functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie18eb7e9cff4053792706cd7c467e1a2b1347345
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 66fe0c43be
Original-Change-Id: I529c67cf20253cf819d1c13849300788104b083c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19827
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531711
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The supported "G41C-GS" with a nuvoton nct6776 superio is actually
G41C-GS R2.0, which is different with the more easily-found revision
G41C-GS (R1.0) with Winbond W83627DHG superio, and should be ported
separately.
Photos for the two revision:
R1.0: https://web.archive.org/web/20160915160553/http://www.asrock.com/mb/photo/G41C-GS(L1).jpg
R2.0: https://web.archive.org/web/20160717203810/http://www.asrock.com/mb/photo/G41C-GS%20R2.0(L2).jpg
BUG=none
BRANCH=none
TEST=none
Change-Id: If8236eacdc35b3b22d813265e678f0321878bfee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1517bab693
Original-Change-Id: If60a694bcf0652ab32c0ac75ceec7e27e11fe9eb
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19980
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/531710
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Rename these two Macros to help use Common Code -
ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS
ACPI_PMIO_SIZE --> ACPI_BASE_SIZE
BUG=none
BRANCH=none
TEST=none
Change-Id: I2d61fac058531f45d9133578c818440ed4c5ea93
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9e55ff6a87
Original-Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20038
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531709
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch enables ACPI timer emulation on all the logical cpus.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init.
Change-Id: Ic11a9038769abdca530a7f6fc36695c4638d9487
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f004f66ca7
Original-Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18288
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531708
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch makes SOC files to use common/block/cpu/cpulib.c
file's helper functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia0328783f3365d1ec06dd87b1e744e5c4d4871ec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0a203d13f6
Original-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19566
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531707
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Create Intel Common CPU library code which provides various
CPU related APIs.
This patch adds cpulib.c file which contains various helper
functions to address different CPU functionalities like -
cpu_set_max_ratio(),
cpu_get_flex_ratio(),
cpu_set_flex_ratio(),
cpu_get_tdp_nominal_ratio(),
cpu_config_tdp_levels(),
cpu_set_p_state_to_turbo_ratio(),
cpu_set_p_state_to_nominal_tdp_ratio(),
cpu_set_p_state_to_max_non_turbo_ratio(),
cpu_get_burst_mode_state(),
cpu_enable_burst_mode(),
cpu_disable_burst_mode(),
cpu_enable_eist(),
cpu_disable_eist(),
cpu_enable_untrusted_mode()
BUG=none
BRANCH=none
TEST=none
Change-Id: I14bbfb9d3198ca46470d04edcb74d7d43e709034
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 19b546f48c
Original-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19540
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531706
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=none
BRANCH=none
TEST=Build and boot Reef
Change-Id: Ie3165594c63cf657d4079867b5b2c7fab2cd8649
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6520e01a46
Original-Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20037
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531705
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since get_microcode_info() is aleady searching for the microcode in cbfs,
we can just add a intel_microcode_load_unlocked() call here to update
the microcode. No need to duplicate finding microcode step during
pre_mp_init() function.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id9bb31b2b02dd92dadb76cbd37bf1f5e01b64117
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 97daf98806
Original-Change-Id: I525cab0ecc7826554f0a1209862e6357d1c7a9a6
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20088
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531704
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
FIT is already loading microcode before CPU Reset. So, we need
not update the microcode again in RO FW in bootblock.
But we need to update in RW FW if there is any new ucode version.
So, added the update microcode function in get_microcode_info callback
before MP Init to make sure BSP is using the microcode from cbfs.
BUG=none
BRANCH=none
TEST=Build and Boot poppy
Change-Id: I7665b2f1fc10f625f8535aef1f11a77154dfe2a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 682355ab16
Original-Change-Id: I5606563726c00974f00285acfa435cadc90a085e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20051
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531703
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.
Depthcharge payload loading was sped up by 75ms using this.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icca415dceef9b20728294a890e908905e4208636
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 93d5f40be5
Original-Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20089
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531702
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The fast_spi_cache_bios_region() does the necessary lookup
of BIOS region size, etc. Don't inline the calculation and
just defer to the common piece of code for memory-mapped
spi flash boot.
BUG=none
BRANCH=none
TEST=none
Change-Id: I47744f71cad87b908f8f672930c6c4d1716e04c7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: efc92a86c2
Original-Change-Id: I6c390aa5a57244308016cd59679d8c3ab02031b8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20116
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531701
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
After the MTRR solution has been calculated provide a way
for code to call the same function, fast_spi_cache_bios_region(),
in all stages. This is accomplished by using the ramstage
temporary MTRR support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I05bb30b98455539fe5aed7e25b44bee185918744
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0b34fc6f54
Original-Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20115
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/531700
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like the previous commit allow the declarations of functions to
be exposed to all stages unless ROMCC is employed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I174399f6957768e57d3cc87a157b260632ef45eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ea0497c786
Original-Change-Id: Ie4dfc32f38890938b90ef8e4bc35652d1c44deb5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20114
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531699
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fix line over 80 characters warnings and space after function name
warning.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9a9685c2789b181a23de4d8f253cec5df318d889
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: acd02b5b3f
Original-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3
Original-Signed-off-by: Evelyn Huang <evhuang@google.com>
Original-Reviewed-on: https://review.coreboot.org/19988
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531698
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I3638c07cbbc15025f7bc2b1f573ebc5f7f816fb6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 208587e0f6
Original-Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19795
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531697
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I180d06e3b465e369eb24c1711e48aaf2f59a858a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 46a7178267
Original-Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19796
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531696
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add Intel common systemagent support for romstage and ramstage.
Include soc specific macros need to compile systemagent common code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9af8a5134f382fbfe94945e81adbf15ec97b1a6a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7609c654b1
Original-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c
Original-Signed-off-by: V Sowmya <v.sowmya@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19668
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531695
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
cherry-pick from Chromium, commit 8fbe1e7
On Braswell and Baytrail devices, by userland 'perf top',
observed demanding clocks on __vdso_clock_gettime() since
chromeos_3.18 kernel; besides, evaluated massive calling of
clock_gettime() cost, up to 700 ns in average.
It turns out that Linux kernel of map_vdso() first call of
remap_pfn_range() does not fall into reserve_pfn_range()
due to size parameter, instead it relies on lookup_memtype()
and potentially be failed to be identified as eligible RAM
resource because the function of pat_pagerange_is_ram() actually
walks through root's sibling.
Meanwhile, on current BSW (and BYT) firmware implementation
makes System RAM resources located on child leaf, combining all
of these factors makes the kernel treat the vvar page of vdso
as a uncached-minus one leading slow access in result.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
Original-Change-Id: Iad4ffa542b22073cb087100a95169e2d2a52efcd
Original-Signed-off-by: Harry Pan <harry.pan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/368585
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I60646b49268db162deac8614cc80e5712a358ad0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 43dcbfd855
Original-Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20060
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/531694
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree PCI config based on board spec:
- enable PCIe Root Ports 5 and 9 (wifi and nvme respectively)
- enable PCIe CLKREQ on RP9, disable on RP5
- enable USB OTG
- enable P2SB
Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1
BUG=none
BRANCH=none
TEST=none
Change-Id: I8883f75cc65b56dc22e38ec5513149c0d9205137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: debb785d59
Original-Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19939
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531693
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Needed for UEFI booting via Tianocore;
with PM timer disabled, payload hangs.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0ac172b90f496e44b117e3ec9a3809d7708b85b6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0ff3b73990
Original-Change-Id: I6c65cb9d3e6a10baea4cc1e2d9e94c36fe419561
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19938
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531692
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I34e5babc9b6f059d73d02348ad0fbcff07563527
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d8cd507a6
Original-Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19937
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531691
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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