`libhwbase` is a SPARK library that contains some basic support for i/o
access, debugging, timers. Just what I put around `libgfxinit`, to make
it build standalone.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifba116e967357ed971aecd8a1d1661a493c0ca81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e09f8acdad
Original-Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/16948
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/430675
If compression failed, just store the uncompressed data, which is what
cbfstool does as well.
BUG=chrome-os-partner:62235
BRANCH=none
TEST=none
Change-Id: I41f911169f376be3dab1335d93e1b3ff68ad7377
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b46c4ecaba
Original-Change-Id: I67f51982b332d6ec1bea7c9ba179024fc5344743
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18201
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430741
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia83222824b338692fbcfe67318da1ca7173f46a7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: eee4f6b224
Original-Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18022
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/431292
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The devicetree settings were incorrect in a few places with
respect to the SOC and board design:
- IMVP8 VR workaround is for MP2939 and not MP2949 on Eve
- IccMax values are incorrect according to KBL-Y EDS
- USB2[6] is incorrectly labeled
- I2C touch devices do not need probed as they are not optional
- PCIe Root Port 5 should be enabled
- I2C5 device should not be enabled as it is unused
BUG=chrome-os-partner:58666
TEST=manually tested on Eve board
Change-Id: Ic863b0dce44a2f7f55b15a7a87513edc753d6a3c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 949e34c3ee
Original-Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18200
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431290
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to get quick boot speeds into recovery enable the
feature that allows for a separate recovery MRC cache.
This requires shuffling the FMAP around a bit in order to
provide another region for the recovery MRC cache. To make
that shuffling easier, group the RW components into another
sub-region so it can use relative addresses.
BUG=chrome-os-partner:58666
TEST=manual testing on eve: check that recovery uses the MRC
cache, and that normal mode does too. Check that if cache is
retrained in recovery mode it is also retrained in normal mode.
Also check that events show up in the log when retrain happens.
Change-Id: Id8e62117a9e679ef03e87a8563c377fc2a9a7c20
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: e00365217c
Original-Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18199
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431209
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The lpss_i2c driver is enabled in romstage, so the SOC needs to
export the pre-ram compatible I2C controller info, which for
skylake is in the bootblock/i2c.c file.
This was not causing a compiler error in normal use, but when
adding I2C debug code in romstage it failed to compile.
With this added, I can now do I2C transactions in romstage.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb17a32000c65a5f1577d3897ddaa869ef63ee32
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 4234ca2764
Original-Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18198
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431208
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the keyboard backlight as early in boot as possible to
provide a indication that the BIOS is executing.
Since this is bootblock it can't use the convenience function
for checking for S3 resume so just read the PM1 value from the
SOC and check it directly.
Use a value of 75% for the current system as that is visible
without being full brightness.
BUG=chrome-os-partner:61464
TEST=boot on eve and check that keyboard backlight is enabled
as soon as the SOC starts booting
Change-Id: I80274af9b3e032cc97403a180477b2d4742ad753
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 367c9b328f
Original-Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18197
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/431207
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
They were sized to 32-bit alignment, this grows them to 64 bit-aligned.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie84b2c35b58f186bd8ae993e7ce298332858de05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bb036dcb
Original-Change-Id: I494b942c4866a7912fb48a53f9524db20ac53a8c
Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18165
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430618
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Removes the pre-defined VGA bios file and id because
the build system includes every vgabios.
Also make the VGA output primary by default
BUG=none
BRANCH=none
TEST=none
Change-Id: I851d602b470b1f0b504d07d5fe70fd58f20ae1a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c765ceff9
Original-Change-Id: I87d52ef2d1e151c6e54beba64316fe9043668158
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18181
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430617
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the ME is hidden (most likely because it was disabled), it cannot
be found until activate_me() is called.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifef2392e067c2075fafe6c83a3560dcedb2bf75d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8ad3c7b95
Original-Change-Id: Ie1f65f61eb131577d7254af582e2709660f4da27
Original-Signed-off-by: Dan Elkouby <streetwalrus@codewalr.us>
Original-Reviewed-on: https://review.coreboot.org/18149
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430616
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PP1800_S rail is turned off in S3. However, enabling internal
pullups on the pins which are connected to PP1800_S results in
leakage into the P1800_S rail. Fix this by disabling the internal
pullups on PP1800_S rail pins.
BUG=chrome-os-partner:61968
BRANCH=reef
TEST=measured leakage on PP1800_S rail. Gone with this patch.
Change-Id: I5c9a25ca617078a6ad48fe637abf0f397fda1ff5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa6482e88e
Original-Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808
Original-Signed-off-by: Aaron Duribn <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18189
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430614
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=None
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I0b3ec47e93b064f2195ec59bd9b5b8bc1927b3bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf68f2286c
Original-Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18163
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430612
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per Audio PCH team recommendation the iDisplay Audio/SDIN2
should be disabled to bypass InitializeDisplayAudio() function
call. Display Audio Codec is HDA-Link Codec, which is not
supported in I2S mode
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Tested to verify that InitializeDisplayAudio() does not
get called.
Change-Id: I5900291ca4b2929db3e09277ffc3dce24d8de6fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 32997fb0bc
Original-Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18091
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430611
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
arm-trusted-firmware comes with another firmware for a coprocessor that
isn't AArch64. When building ATF, make sure to pass our arm(32) compiler
for that purpose.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0fb841a8d434389bc665fd6c133465dfcbba1fde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f34ca46fa6
Original-Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18024
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430717
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, it will print the function name as a prefix to the debug
output. Make it so that a null function name won't get printed, so
that it's possible to print little bits of debug output.
BUG=chromium:683391
BRANCH=none
TEST=build_packages --board=reef chromeos-firmware
Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431111
Reviewed-by: Julius Werner <jwerner@chromium.org>
This takes way too long to run - currently about 30 seconds to look
at the entire coreboot tree.
Change-Id: I5edc77bc808665ef9832970f5a6458ffe8c04ee1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e03fbced7
Original-Change-Id: I403934014b422528715ea95ff652babe5e18c88b
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/15976
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430716
This enables USB HID support in the veyron config, since it seems to
work correctly and is needed for interaction with depthcharge on devices
without an embedded keyboard (such as veyron_mickey).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic1ed2987074924fdab987974ad8e5bb7c9006f15
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e7f14bfae
Original-Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/17930
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430715
Audio DMIC PLL needs to be ON in S0ix to support
Wake on Voice. This requires GPIO_79 and GPIO_80
to be configured as IGNORE IOSSTATE. So DMIC CLKs
will be ON in S0ix.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id6ddb380477762b37fe0b8fdcac762033048438b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0eae6112f
Original-Change-Id: If91045a8664ce853366b670b9db38d620818fbab
Original-Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18155
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430713
Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not be started at all.
The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the
build and boot issue with this change.
Besides that, rename the romstage_after_verstage to romstage_c_entry
in more appropriate naming convention after this fix.
Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0),
romstage can be started successfully.
BUG=none
BRANCH=none
TEST=none
Change-Id: I95a45a090b4a335fa8655c89fbede13d011bb321
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8e34b2c44
Original-Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17976
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/430735
This fixes the generic timer driver to get the current tick from the
high register, so that comparison with the high count value (obtained
previously from the same register) has a chance to succeed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/427823
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
There was some ongoing development on the generic timer driver after it
was merged into CrOS libpayload, so fetch that.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:427823
Change-Id: I78c38eb8c8a3aca66a08e702978a7290a26fd3d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427822
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
This was already done in upstream when the patch was taken over.
Eliminate the difference.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14545c81d0311130e6756c128b2653a5f92efe16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427821
It's already available in commonlib/helpers.h
BUG=none
BRANCH=none
TEST=things still build
Change-Id: Ib6e3eff82eb4fe6f3aef2065f5c2f7ada11e9e25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427820
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The coreboot builder makes use of the pre defined configuration
files by executing abuild with -d option. These configuration
files contain a basic configuration.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iea4b296f7754a89ea3c19d871003a97093c10fa1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96326d3aef
Original-Change-Id: I41470fe7aaa0fdae545ad9d702326a202d0d2312
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18161
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430182
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
It's a BSD function, also, we missed to include `endian.h`.
Just including `endian.h` doesn't fix the problem for everyone.
Instead of digging deeper, just use our own endian-conversion from
`commonlib`.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ideec790c2ef2f5a97908a589908d8666e61bab65
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 607796a4ff
Original-Change-Id: Ia781b2258cafb0bcbe8408752a133cd28a888786
Original-Reported-by: Werner Zeh <werner.zeh@siemens.com>
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/18157
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/430181
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Previously SeaBIOS's default was used (1). This patch defaults to
coreboot's console level instead which is approximately the same
verbosity as SeaBIOS and thus what a user would probably expect.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic99aad03d625b6d81ce0a047c35a39074985f3d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c48d791506
Original-Change-Id: If79e5f40c9380bb527f870eeb7d0cb43faf00beb
Original-Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Original-Reviewed-on: https://review.coreboot.org/18051
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/430180
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The script now automatically discovers the original branch (if known)
and configures itself appropriately.
Additionally, commit messages for changes coming _from_ upstream will
be prefixed with "UPSTREAM: ".
With the optional --cros argument, it also adds a BUG/BRANCH/TEST block
at the right place in the commit message (right above the metadata) if
one doesn't already exist.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7ad3fb5317d9e3090f43ea983fcfb2ab099c43a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f27edd377
Original-Change-Id: I81864ddca62fd99a9eb905d7075e5b53f58c4eb5
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18135
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430179
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
SPI controller need to access flash descriptors/SFDP during s0ix exit,
so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
GPIO_106.
BUG=chrome-os-partner:61370
BRANCH=reef
TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
content.
Change-Id: Ibeb71637b19c646a3390e98d083ae579144cb31c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8b89252f8a
Original-Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18137
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430178
Tested-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.
Variants contain board specific data:
- DPTF ACPI components
- I2C ACPI devices
- RAM config / SPD data
- devicetree config
- GPIOs
- board-specific HW components (e.g., LAN)
Additionally, some minor cleanup/changes were made:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
The existing enguarde and ninja boards are removed.
Variant setup modeled after google/auron
BUG=none
BRANCH=none
TEST=none
Change-Id: I9129c3d3eda15c1e91ff5bfd0aa5f9f891a2636c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce0a564198
Original-Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18129
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430177
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The new name and location make more sense:
- The instruction used to call into machine mode isn't called "ecall"
anymore; it's mcall now.
- Having SBI_ in the name is slightly wrong, too: these numbers are not
part of the Supervisor Binary Interface, they are just used to
forward SBI calls (they could be renumbered arbitrarily without
breaking an OS that's run under coreboot).
Also remove mcall_dev_{req,resp} and the corresponding mcall numbers,
which are no longer used.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71a96971f46d515a66d5f77497b40d891c1b5fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c5ebb1d005
Original-Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18146
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/430174
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
1. Disable WP
2. Pass SD card detect info in ACPI
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Verified that OS is able to detect SD card and read/write to it.
Change-Id: Id16f21dd70798b2e1c6e7af1d163e7089b66b46c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d093e4a387
Original-Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18138
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430172
poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: I80eab8bc6fb486bab959ab308c93d1d3031247bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4a159706e
Original-Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18133
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430171
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
