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UPSTREAM: soc/intel/skylake: Include I2C code in romstage

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The lpss_i2c driver is enabled in romstage, so the SOC needs to
export the pre-ram compatible I2C controller info, which for
skylake is in the bootblock/i2c.c file.

This was not causing a compiler error in normal use, but when
adding I2C debug code in romstage it failed to compile.
With this added, I can now do I2C transactions in romstage.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ieb17a32000c65a5f1577d3897ddaa869ef63ee32
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 4234ca2764
Original-Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18198
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431208
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2017-01-21 16:55:03 -08:00 • committed by chrome-bot
parent 56428572c3
commit e5772aebf8
1 changed files with 1 additions and 0 deletions
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src/soc/intel/skylake/Makefile.inc
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@ -38,6 +38,7 @@ verstage-y += spi.c
romstage-y += flash_controller.c
romstage-y += gpio.c
romstage-y += bootblock/i2c.c
romstage-y += memmap.c
romstage-y += monotonic_timer.c
romstage-y += me.c