- VIA 686 cleanups from the A7M code (it now works in a different pci slot).
- Update of assembly printing routines to use the debug levels:
TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR.
It's more verbose but now the controls are the same as with the C code.
- Break off of loglevel.h from printk.h. loglevel.h is safe for both
the assembly routines and the C code to include.
- Next round of commits for the supermicro p4dc6
- SMP setup updates (Rons board is broken)
I now allow the other SMP processors to report their existence.
I really need to add a minimum time to run but that hasn't happened yet.
- SMP per motherboard table of apicids, as the assumption that they
would always be 0 & 1 with only two cpus fails.
- RDRAM setup updates. The code isn't done but it now works on more
than one board at a time.
- More cacheram work. Minor bug fixes and some macros to use it from C.
- Entry point changes so we no longer have to jump over our gdt.
- Added/Audited the cpufixup for the i786
- IDE intialization for the 82801 ich2 chip.
This also includes a bunch of my pending work including
- Updated serial code so we can compile in different serial port speeds
- Updates to the build system so that:
- Makefile.settings holds all of the settings of the config variables
- ldoptions and cpuflags are generated automatically with perl scripts
- src/config/Config holds all of the architecture neutral make file settings
- Initial work on the P4 including how to use cache as ram
- Update to the ioapic code for the P4 because it delivers irqs on the system
bus instead of an out of band bus
- Updated version of printf that doesn't need an intermediate buffer
- logbuf_subr now handles the case when we want to use a log buffer
- video_subr handles the preliminary code for writing to a video device.
- Pending changes for the L440GX are merged in as well (hopefully I haven't
messed then up since they were written).
This actually can result in bad RPS sizes in register 74.w (RPS)
for slots where
there is no DRAM installed. This really does not matter since the actual
access to DRAM is controlled elsewhere. If there is not DRAM in a slot,
then that piece of the RPS register will never be used.
