mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
New raminit.inc
This commit is contained in:
Ronald G. Minnich
parent
492ad3aaed
commit
1da6fe55ec
1 changed files with 176 additions and 46 deletions
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@ -26,12 +26,34 @@ jmp intel_815_out
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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// trashed : ax, bx, dx, sp
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#define NEWLINE \
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TTYS0_TX_CHAR($'\r') ;\
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TTYS0_TX_CHAR($'\n')
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#define PRINT_REG(reg) \
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TTYS0_TX_HEX8($reg) ; \
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TTYS0_TX_CHAR($':') ; \
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mov $reg, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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TTYS0_TX_HEX8(%al) ; \
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NEWLINE
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#define PRINT_REG_WORD(reg) \
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TTYS0_TX_HEX8($reg) ; \
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TTYS0_TX_CHAR($':') ; \
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mov $reg, %eax ; \
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PCI_READ_CONFIG_WORD ; \
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andl $0xffff, %eax ; \
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TTYS0_TX_HEX32(%eax) ; \
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NEWLINE
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#define FIRST_NORMAL_REFERENCE()
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#define SPECIAL_FINISHUP()
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#define RAM_COMMAND_NORMAL 0x0 // self refresh
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#define RAM_COMMAND_NORMAL_0 0x1 // 15.6 us
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#define RAM_COMMAND_NORMAL_1 0x2 // 7.8 us
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#define RAM_COMMAND_NORMAL_1 0x2 // 7.8 us.
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#define RAM_COMMAND_NORMAL_2 0x3 // 1.28
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#define RAM_COMMAND_NOP 0x4
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#define RAM_COMMAND_PRECHARGE 0x5
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@ -50,12 +72,49 @@ jmp intel_815_out
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#define ENABLE_REFRESH()
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#define REG_PCICMD0 0x04
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#define REG_PCICMD1 0x05
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#define REG_PCICMD1 0x05
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#define REG_PCISTS0 0x06
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#define REG_PCISTS1 0x07
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#define REG_SVID0 0x2c
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#define REG_SVID1 0x2d
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#define REG_SID0 0x2e
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#define REG_SID1 0x2f
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#define REG_MCHCFG 0x50
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#define MCHCFG_CLT 0x40 // CLT (Cpu Latency Timer)
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#define MCHCFG_LMFS_MASK 0x10 // local memory frequency mask
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#define MCHCFG_LMFS_133 0x10 // 133Mhz
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#define MCHCFG_LMFS_100 0x00 // 100Mhz
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#define MCHCFG_DPCP_MASK 0x08 // dram paging policy mask
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#define MCHCFG_DPCP_0 0x00 // precharge bank at page miss
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#define MCHCFG_DPCP_1 0x08 // precharge all
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#define MCHCFG_SMFS_MASK 0x04 // memory frequency mask
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#define MCHCFG_SMFS_133 0x04 // 133Mhz
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#define MCHCFG_SMFS_100 0x00 // 100Mhz
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#define REG_APCONT 0x51
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#define REG_DRP 0x52
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#define REG_DRAMT 0x53
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#define DRAMT_DCT 0x10
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#define DRAMT_HACQS 0x08 // host aperture cycle queue slot
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#define DRAMT_CL_MASK 0x04 // CAS# latency mask
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#define DRAMT_CL_2 0x04 // 2 SCLK
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#define DRAMT_CL_3 0x00 // 3 SCLK
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#define DRAMT_SRCD 0x02 // RAS# latency. 0 = 3 SCLK, 1 = 2 SCLK
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#define DRAMT_SRP 0x01 // RAS# precharge. 0 = 3 SCLK, 1 = 2 SCLK
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#define REG_DRP2 0x54
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#define REG_FDHC 0x58
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#define FDHC_HEN 0x80 // 0 = no hole, 1 = 15-16MB hole enable.
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#define REG_PAM0 0x59
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#define REG_PAM1 0x5A
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#define REG_PAM2 0x5B
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@ -64,20 +123,36 @@ jmp intel_815_out
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#define REG_PAM5 0x5E
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#define REG_PAM6 0x5F
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#define REG_SMRAM 0x70
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#define REG_BUFF_SC0 0x92
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#define REG_BUFF_SC1 0x93
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#define REG_MISCC 0x72
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#define MISCC_BYPASS 0x2000
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#define MISCC_CPCME 0x0800
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#define MISCC_WPTC_MASK 0x0030
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#define MISCC_WPTC_100 0x0010
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#define MISCC_WPTC_133 0x0020
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#define REG_BUFF_SC 0x92
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#define REG_BUFF_SC2 0x94
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#define REG_SM_RCOMP 0x98
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#define REG_SM0 0x9c
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#define REG_SM1 0x9d
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#define REG_SM2 0x9e
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#define REG_SM3 0x9f
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/* default values for config registers */
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ram_set_registers:
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CS_WRITE_BYTE(REG_PCICMD1, 0x00) // disable SERR#
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CS_WRITE_BYTE(REG_PCISTS1, 0x20) // new.
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CS_WRITE_BYTE(REG_SVID0, 0x86)
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CS_WRITE_BYTE(REG_SVID1, 0x80) // new
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CS_READ_BYTE(REG_MCHCFG)
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TTYS0_TX_HEX32(%eax)
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// CS_WRITE_BYTE(REG_MCHCFG, 0x50)
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CS_WRITE_BYTE(REG_DRP, 0x00)
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CS_WRITE_BYTE(REG_SID0, 0x30)
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CS_WRITE_BYTE(REG_SID1, 0x11) // new
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CS_WRITE_BYTE(REG_PCICMD1, 0x00) // disable SERR#
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CS_WRITE_BYTE(REG_APCONT, 0x00)
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CS_WRITE_BYTE(REG_DRP2, 0x00)
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CS_WRITE_BYTE(REG_DRAMT, 0x08)
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CS_WRITE_BYTE(REG_FDHC, 0x00)
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CS_WRITE_BYTE(REG_PAM0, 0x00)
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CS_WRITE_BYTE(REG_PAM1, 0x00)
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@ -87,25 +162,62 @@ ram_set_registers:
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CS_WRITE_BYTE(REG_PAM5, 0x00)
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CS_WRITE_BYTE(REG_PAM6, 0x00)
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CS_WRITE_BYTE(REG_SMRAM, 0x00)
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CS_WRITE_BYTE(REG_BUFF_SC0, 0xff)
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CS_WRITE_BYTE(REG_BUFF_SC1, 0xff)
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CS_WRITE_BYTE(REG_SM0, 0x46)
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CS_WRITE_BYTE(REG_SM1, 0x83)
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CS_WRITE_BYTE(REG_SM2, 0xc4)
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CS_WRITE_BYTE(REG_SM3, 0x00)
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RET_LABEL(ram_set_registers)
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ram_set_spd_registers:
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// TODO: SPD
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CS_WRITE_BYTE(REG_DRP, 0x0E) // 256M, SS, DIMM0
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CS_WRITE_BYTE(REG_DRAMT, 0x00) //
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CS_WRITE_BYTE(REG_MCHCFG, 0x44)
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CS_WRITE_BYTE(0x72, 0x28)
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CS_WRITE_BYTE(0x73, 0x20)
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// CS_WRITE_WORD(REG_MISCC, MISCC_BYPASS | MISCC_CPCME | MISCC_WPTC_133)
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// bypass for 133Mhz.
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// write power throttle
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// 400MB/sec - 133Mhz
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// drp
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CS_WRITE_BYTE(REG_DRP, 0x0E) // 256M, SS, DIMM0
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// dramt
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CS_WRITE_BYTE(REG_DRAMT, 0x18)
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// buff_sc
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// CS_WRITE_WORD(REG_BUFF_SC, 0xffdf) // rows 0/1 - 1.7x8 load
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CS_WRITE_BYTE(0x92, 0xae)
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CS_WRITE_BYTE(0x93, 0x3e)
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// CS_WRITE_WORD(REG_BUFF_SC2, 0xfffe) // row 0 - 2.7x8 load
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CS_WRITE_BYTE(0x94, 0xfe)
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CS_WRITE_BYTE(0x95, 0xff)
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// SM_RCOMP
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CS_WRITE_BYTE(0x98, 0x43)
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CS_WRITE_BYTE(0x99, 0x80)
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CS_WRITE_BYTE(0x9a, 0x43)
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CS_WRITE_BYTE(0x9b, 0x80)
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RET_LABEL(ram_set_spd_registers)
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ram_enable_1: .string "\r\nRam Enable 1\r\n"
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ram_enable_2: .string "\r\nRam Enable 2\r\n"
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ram_enable_3: .string "\r\nRam Enable 3\r\n"
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ram_enable_4: .string "\r\nRam Enable 4\r\n"
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ram_enable_5: .string "\r\nRam Enable 5\r\n"
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ram_fail: .string "\r\n--- FAILED TO INITIALIZE \r\n"
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ram_pass: .string "\r\n--- SDRAM TEST PASSED \r\n"
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ram_enable_1: .string "Ram Enable 1\r\n"
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ram_enable_2: .string "Ram Enable 2\r\n"
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ram_enable_3: .string "Ram Enable 3\r\n"
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ram_enable_4: .string "Ram Enable 4\r\n"
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ram_enable_5: .string "Ram Enable 5\r\n"
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ram_fail: .string "--- FAILED TO INITIALIZE \r\n"
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ram_pass: .string "--- SDRAM TEST PASSED \r\n"
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#define DO_READ(addr) \
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movl addr, %eax ; \
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movl (%eax), %ebx
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@ -116,42 +228,48 @@ ram_pass: .string "\r\n--- SDRAM TEST PASSED \r\n"
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movl %ebx, (%eax)
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#define IODELAY outb %al, $0x80 // took approximately 1us
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mydelay:
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mov $2000, %ecx
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delay_loop:
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IODELAY
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decl %ecx
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jne delay_loop
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RETSP
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#define MYDELAY(x) \
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mov x, %ecx ; \
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1: IODELAY ; \
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loop 1b
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#define RAMREAD DO_READ($0x0)
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enable_sdram:
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// Enterring NOP command enable mode
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TTYS0_TX_STRING($ram_enable_1)
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SET_RAM_COMMAND(RAM_COMMAND_NOP)
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DO_READ($0x0) // do read from sdram address 0
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CALLSP(mydelay) // wait a while (minimal 200us)
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RAMREAD
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MYDELAY($400) // wait a while (minimal 200us)
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// Precharge all
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TTYS0_TX_STRING($ram_enable_2)
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SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE)
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// DO_READ($0x0) // do read from sdram address 0
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DO_READ($0x2000)
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RAMREAD
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// 8 auto refresh command / "CAS before RAS"
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// 8 auto refresh command "CAS before RAS"
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TTYS0_TX_STRING($ram_enable_3)
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SET_RAM_COMMAND(RAM_COMMAND_CBR)
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mov $8, %ecx
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1:
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DO_READ($0x0)
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// IODELAY
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TTYS0_TX_CHAR($'.')
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dec %ecx
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jne 1b
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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RAMREAD
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MYDELAY($100)
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// Mode register set
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TTYS0_TX_STRING($ram_enable_4)
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SET_RAM_COMMAND(RAM_COMMAND_MRS)
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@ -174,16 +292,28 @@ enable_sdram:
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orl $0x2a, %eax
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shll $3, %eax
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movl (%eax), %ebx // MRS comand.
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movl (%eax), %ebx // MRS comand to sdram
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// TTYS0_TX_HEX32(%eax)
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// Normal operation mode
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TTYS0_TX_STRING($ram_enable_5)
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SET_RAM_COMMAND(RAM_COMMAND_NORMAL_1)
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SET_RAM_COMMAND(RAM_COMMAND_NORMAL_0) // SPD: 12 (refresh rate)
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DO_READ($0x0)
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/*
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DO_WRITE($0x0, $0x0)
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DO_READ($0x0)
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TTYS0_TX_HEX32(%eax)
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NEWLINE
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DO_WRITE($0xff, $0xff)
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DO_READ($0xff)
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TTYS0_TX_HEX32(%eax)
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NEWLINE
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*/
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#if 0
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// Now setup is done. we can write to SDRAM
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// test this.
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