Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

technoland sbc 710 support

Browse source
This commit is contained in:
Ronald G. Minnich 2001-10-16 22:23:29 +00:00
parent 933ee4a04e
commit 954c2fd8e2
5 changed files with 229 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
src/mainboard/technoland/sbc710/Config Normal file
View file

@ -0,0 +1,32 @@
arch i386
mainboardinit cpu/i386/entry16.inc
ldscript cpu/i386/entry16.lds
mainboardinit cpu/i386/reset16.inc
ldscript cpu/i386/reset16.lds
# mainboardinit superio/NSC/pc87309/setup_serial.inc
mainboardinit pc80/serial.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc
#superio NSC/pc87309
nsuperio winbond/w83977ef
nsuperio winbond/w83877tf
option ENABLE_FIXED_AND_VARIABLE_MTRRS
option PIIX4_DEVFN=0x38
option NO_KEYBOARD
option HAVE_PIRQ_TABLE
option ZKERNEL_START=0xfffc0000
option ZKERNEL_MASK=0x7f
option L440BX
object mainboard.o
object irq_tables.o
cpu p6
cpu p5

23
src/mainboard/technoland/sbc710/config.example Normal file
View file

@ -0,0 +1,23 @@
# Sample config file for technoland sbc710
target tlsbc710
mainboard technoland/sbc710
# Enable Serial Console for debugging
option SERIAL_CONSOLE
option NO_KEYBOARD
# Enable MicroCode update and L2 Cache init for PII and PIII
option UPDATE_MICROCODE
#option CONFIGURE_L2_CACHE
option INBUF_COPY
option DEFAULT_CONSOLE_LOGLEVEL=9
option DEBUG
# Path to your kernel (vmlinux)
linux ~/src/bios/linux-2.4.7-sis
# Kernel command line parameters
commandline root=/dev/hda6 console=ttyS0,115200 FS_MODE=ro hda=flash hdb=flash

5
src/mainboard/technoland/sbc710/do_ramtest.inc Normal file
View file

@ -0,0 +1,5 @@
mov $0x00000000, %eax
mov $0x0009ffff, %ebx
mov $16, %ecx
CALLSP(ramtest)

163
src/mainboard/technoland/sbc710/irq_tables.c Normal file
View file

@ -0,0 +1,163 @@
#include <subr.h>
#include <arch/pirq_routing.h>
/*
* This table must be located between 0x000f0000 and 0x000fffff.
* By defining it as a const it gets located in the code segment
* and therefore inside the necessary 64K block. -tds
*/
#define USB_DEVFN (PIIX4_DEVFN+2)
#define SUM_REST 0x00 /* ...just happens to be 0 */
#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN))
// In spite of the comment below I have located this in the
// gigabit tree until we work this all out -- RGM
/*
* This table should work for most systems using the PIIX4
* southbridge that have 4 PCI slots.
*
* I recall that the 440GX board that Ron was using had
* the PIIX4 at a different location. This will effect the
* devfn of the router and USB controller as well as the
* checksum. Hopefully the defines will allow this to
* be a bit more portable.
* -tds
*/
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*5, /* u16 size - size of entire table struct */
0, /* u8 rtr_bus - router bus */
PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */
0x0e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */
0x8086, /* u16 rtr_vendor - router vendor id */
0x7110, /* u16 rtr_devfn - router device id */
0, /* u8 miniport_data - "crap" */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
/* struct irq_info slots[0] */
{
{
0, /* u8 bus */
USB_DEVFN, /* u8 devfn for USB controller */
{
{
0x00, /* u8 link - IRQ line ID */
0x0000, /* u16 bitmap - Available IRQs */
},
{
0x00, /* u8 link - IRQ line ID */
0x0000, /* u16 bitmap - Available IRQs */
},
{
0x00, /* u8 link - IRQ line ID */
0x0000, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
0, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x40, /* u8 devfn for PCI slot 1 */
{
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
1, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x48, /* u8 devfn for PCI slot 2 */
{
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
2, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x50, /* u8 devfn for PCI slot 3 */
{
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
3, /* u8 slot */
0, /* u8 rfu */
},
{
0, /* u8 bus */
0x58, /* u8 devfn for PCI slot 4 */
{
{
0x63, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x60, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x61, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
},
{
0x62, /* u8 link - IRQ line ID */
0xdef8, /* u16 bitmap - Available IRQs */
}
},
4, /* u8 slot */
0, /* u8 rfu */
}
}
};

6
src/mainboard/technoland/sbc710/mainboard.c Normal file
View file

@ -0,0 +1,6 @@
void
mainboard_fixup()
{
void southbridge_fixup(void);
southbridge_fixup();
}