Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

- Delayed commit of code for the ASUS A7M motherboard

Browse source 
- VIA 686 cleanups from the A7M code (it now works in a different pci slot).
- Update of assembly printing routines to use the debug levels:
  TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR.
  It's more verbose but now the controls are the same as with the C code.
- Break off of loglevel.h from printk.h.  loglevel.h is safe for both
  the assembly routines and the C code to include.
- Next round of commits for the supermicro p4dc6
- SMP setup updates (Rons board is broken)
  I now allow the other SMP processors to report their existence.
  I really need to add a minimum time to run but that hasn't happened yet.
- SMP per motherboard table of apicids, as the assumption that they
  would always be 0 & 1 with only two cpus fails.
- RDRAM setup updates.  The code isn't done but it now works on more
  than one board at a time.
- More cacheram work.  Minor bug fixes and some macros to use it from C.
- Entry point changes so we no longer have to jump over our gdt.
- Added/Audited the cpufixup for the i786
- IDE intialization for the 82801 ich2 chip.
This commit is contained in:
Eric W. Biederman 2001-11-13 03:43:37 +00:00
parent 7ca28e1b0f
commit d96aab9e06
79 changed files with 2032 additions and 733 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
Documentation/Config
View file

@ -260,8 +260,9 @@ Here is a sample crt0.S from the existing LinuxBIOS.
#include "VIA_VT82C686A.S"
#include "serial.S"
#include <arch/i386/lib/console.inc>
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -284,7 +285,7 @@ Here is a sample crt0.S from the existing LinuxBIOS.
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -296,7 +297,7 @@ Here is a sample crt0.S from the existing LinuxBIOS.
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -320,7 +321,7 @@ Here is a sample crt0.S from the existing LinuxBIOS.
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

9
romimages/RON_VIA_SPD/crt0.S
View file

@ -32,11 +32,12 @@
#include <superio/via/vt82c686/setup_serial.inc>
#include <pc80/serial.inc>
#include <arch/i386/lib/console.inc>
#include <pc80/i8259.inc>
/*
*/
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -63,7 +64,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -75,7 +76,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -99,7 +100,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

9
romimages/RON_VT5259A/crt0.S
View file

@ -32,11 +32,12 @@
#include <superio/via/vt82c686/setup_serial.inc>
#include <pc80/serial.inc>
#include <arch/i386/lib/console.inc>
#include <pc80/i8259.inc>
/*
*/
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -63,7 +64,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -75,7 +76,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -99,7 +100,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

9
romimages/RON_VT5426/crt0.S
View file

@ -29,11 +29,12 @@
#include <superio/via/vt8231/setup_serial.inc>
#include <pc80/serial.inc>
#include <arch/i386/lib/console.inc>
#include <pc80/i8259.inc>
/*
*/
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -58,7 +59,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -70,7 +71,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -94,7 +95,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

26
src/arch/i386/config/crt0.base
View file

@ -26,9 +26,7 @@
CRT0_PARAMETERS
#if defined(SERIAL_CONSOLE) && (DEFAULT_CONSOLE_LOGLEVEL >= 7)
TTYS0_TX_STRING($str_after_ram)
#endif
CONSOLE_DEBUG_TX_STRING($str_after_ram)
/* clear boot_complete flag */
xorl %ebp, %ebp
@ -75,9 +73,22 @@ __main:
/* set new stack */
movl $_estack, %esp
#ifdef SMP
/* Get the cpu id */
movl $APIC_DEFAULT_BASE, %edi
movl APIC_ID(%edi), %eax
shrl $24, %eax
/* Get the cpu index (MAX_CPUS on error) */
movl $-4, %ebx
1: addl $4, %ebx
cmpl $(MAX_CPUS << 2), %ebx
je 2
cmpl %eax, EXT(initial_apicid)(%ebx)
jne 1b
2: shrl $2, %ebx
/* Now compute the appropriate stack */
movl %ebx, %eax
movl $STACK_SIZE, %ebx
mull %ebx
subl %eax, %esp
@ -96,9 +107,7 @@ __main:
*/
intel_chip_post_macro(0xfe) /* post fe */
#if defined(SERIAL_CONSOLE) && (DEFAULT_CONSOLE_LOGLEVEL >= 7)
TTYS0_TX_STRING($str_pre_main)
#endif
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* memory is up. Let\'s do the rest in C -- much easier. */
@ -115,8 +124,7 @@ __main:
hlt
jmp .Lhlt
ttyS0_test: .string "\r\n\r\nHello world!!\r\n"
.section ".rodata"
str_after_ram: .string "Ram Initialize?\r\n"
str_after_copy: .string "after copy?\r\n"
str_pre_main: .string "before main\r\n"
newline: .string "\r\n"
.previous

4
src/arch/i386/config/ldscript.base
View file

@ -88,8 +88,8 @@ SECTIONS
}
.stack (.) : {
_stack = .;
/* Reserve 64k stack for each possible cpu */
. = ((MAX_CPUS) * (STACK_SIZE));
/* Reserve a stack for each possible cpu, +1 extra */
. = ((MAX_CPUS * STACK_SIZE) + STACK_SIZE) ;
_estack = .;
}

13
src/arch/i386/include/arch/cache_ram.h Normal file
View file

@ -0,0 +1,13 @@
#ifndef CACHE_RAM_H
#define CACHE_RAM_H
#ifndef CACHE_RAM_BASE
#define CACHE_RAM_BASE 0
#endif
#define CACHE_RAM_SEG_BASE (CACHE_RAM_BASE - _RAMBASE)
#define RAM(type, addr) (*((type *)((unsigned char*)((addr) - CACHE_RAM_SEG_BASE))))
#define RAM_ADDR( addr) ((void *)((addr) - CACHE_RAM_BASE))
#endif /* CACHE_RAM_H */

2
src/arch/i386/include/arch/smp/mpspec.h
View file

@ -267,6 +267,8 @@ unsigned char smp_compute_checksum(void *v, int len);
void smp_write_floating_table(void *v);
void write_smp_table(void *v, unsigned long *processor_map);
/* A table (per mainboard) listing the initial apicid of each cpu. */
extern unsigned long initial_apicid[MAX_CPUS];
#else /* HAVE_MP_TABLE */
#define CPU_ENABLED 1 /* Processor is available */

526
src/arch/i386/lib/console.inc Normal file
View file

@ -0,0 +1,526 @@
#include <loglevel.h>
jmp console0
console_test: .string "\r\n\r\nLinuxBIOS starting...\r\n"
/* uses: ax, dx */
#if defined(SERIAL_CONSOLE)
#define __CONSOLE_INLINE_TX_AL TTYS0_TX_AL
#endif
/* uses: esp, ax, dx */
#define __CONSOLE_TX_CHAR(byte) \
mov byte, %al ; \
CALLSP(console_tx_al)
/* uses: ax, dx */
#define __CONSOLE_INLINE_TX_CHAR(byte) \
mov byte, %al ; \
__CONSOLE_INLINE_TX_AL
/* uses: esp, ax, edx */
#define __CONSOLE_TX_HEX8(byte) \
mov byte, %al ; \
CALLSP(console_tx_hex8)
/* uses: byte, ax, dx */
#define __CONSOLE_INLINE_TX_HEX8(byte) \
mov byte, %al ; \
shr $4, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
mov byte, %al ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL
/* uses: esp, eax, ebx, dx */
#define __CONSOLE_TX_HEX32(lword) \
mov lword, %eax ; \
CALLSP(console_tx_hex32)
/* uses: eax, lword, dx */
#define __CONSOLE_INLINE_TX_HEX32(lword) \
mov lword, %eax ; \
shr $28, %eax ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
shr $24, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
shr $20, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
shr $16, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
shr $12, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
shr $8, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
shr $4, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL ; \
; \
mov lword, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
__CONSOLE_INLINE_TX_AL
/* uses: esp, ebx, ax, dx */
#define __CONSOLE_TX_STRING(string) \
mov string, %ebx ; \
CALLSP(console_tx_string)
/* uses: ebx, ax, dx */
#define __CONSOLE_INLINE_TX_STRING(string) \
movl string, %ebx ; \
10: movb (%ebx), %al ; \
incl %ebx ; \
testb %al, %al ; \
jz 11f ; \
__CONSOLE_INLINE_TX_AL ; \
jmp 10b ; \
11:
#define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_EMERG_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_EMERG_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_EMERG_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_EMERG_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_EMERG_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_EMERG_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_EMERG_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_ALERT_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_ALERT_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_ALERT_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_ALERT_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_ALERT_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_ALERT_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_ALERT_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_ALERT_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_CRIT_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_CRIT_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_CRIT_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_CRIT_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_CRIT_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_CRIT_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_CRIT_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_CRIT_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_ERR_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_ERR_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_ERR_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_ERR_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_ERR_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_ERR_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_ERR_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_ERR_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_WARNING_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_WARNING_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_WARNING_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_WARNING_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_WARNING_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_WARNING_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_WARNING_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_WARNING_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_NOTICE_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_NOTICE_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_NOTICE_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_NOTICE_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_NOTICE_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_INFO_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_INFO_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_INFO_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_INFO_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_INFO_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_INFO_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_INFO_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_INFO_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_DEBUG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_DEBUG_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_DEBUG_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_DEBUG_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_DEBUG_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#define CONSOLE_SPEW_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte)
#define CONSOLE_SPEW_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte)
#define CONSOLE_SPEW_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte)
#define CONSOLE_SPEW_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte)
#define CONSOLE_SPEW_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword)
#define CONSOLE_SPEW_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword)
#define CONSOLE_SPEW_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
#if ASM_CONSOLE_LOGLEVEL <= BIOS_SPEW
#undef CONSOLE_EMERG_TX_CHAR
#undef CONSOLE_EMERG_INLINE_TX_CHAR
#undef CONSOLE_EMERG_TX_HEX8
#undef CONSOLE_EMERG_INLINE_TX_HEX8
#undef CONSOLE_EMERG_TX_HEX32
#undef CONSOLE_EMERG_INLINE_TX_HEX32
#undef CONSOLE_EMERG_TX_STRING
#undef CONSOLE_EMERG_INLINE_TX_STRING
#define CONSOLE_EMERG_TX_CHAR(byte)
#define CONSOLE_EMERG_INLINE_TX_CHAR(byte)
#define CONSOLE_EMERG_TX_HEX8(byte)
#define CONSOLE_EMERG_INLINE_TX_HEX8(byte)
#define CONSOLE_EMERG_TX_HEX32(lword)
#define CONSOLE_EMERG_INLINE_TX_HEX32(lword)
#define CONSOLE_EMERG_TX_STRING(string)
#define CONSOLE_EMERG_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_ALERT
#undef CONSOLE_ALERT_TX_CHAR
#undef CONSOLE_ALERT_INLINE_TX_CHAR
#undef CONSOLE_ALERT_TX_HEX8
#undef CONSOLE_ALERT_INLINE_TX_HEX8
#undef CONSOLE_ALERT_TX_HEX32
#undef CONSOLE_ALERT_INLINE_TX_HEX32
#undef CONSOLE_ALERT_TX_STRING
#undef CONSOLE_ALERT_INLINE_TX_STRING
#define CONSOLE_ALERT_TX_CHAR(byte)
#define CONSOLE_ALERT_INLINE_TX_CHAR(byte)
#define CONSOLE_ALERT_TX_HEX8(byte)
#define CONSOLE_ALERT_INLINE_TX_HEX8(byte)
#define CONSOLE_ALERT_TX_HEX32(lword)
#define CONSOLE_ALERT_INLINE_TX_HEX32(lword)
#define CONSOLE_ALERT_TX_STRING(string)
#define CONSOLE_ALERT_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_CRIT
#undef CONSOLE_CRIT_TX_CHAR
#undef CONSOLE_CRIT_INLINE_TX_CHAR
#undef CONSOLE_CRIT_TX_HEX8
#undef CONSOLE_CRIT_INLINE_TX_HEX8
#undef CONSOLE_CRIT_TX_HEX32
#undef CONSOLE_CRIT_INLINE_TX_HEX32
#undef CONSOLE_CRIT_TX_STRING
#undef CONSOLE_CRIT_INLINE_TX_STRING
#define CONSOLE_CRIT_TX_CHAR(byte)
#define CONSOLE_CRIT_INLINE_TX_CHAR(byte)
#define CONSOLE_CRIT_TX_HEX8(byte)
#define CONSOLE_CRIT_INLINE_TX_HEX8(byte)
#define CONSOLE_CRIT_TX_HEX32(lword)
#define CONSOLE_CRIT_INLINE_TX_HEX32(lword)
#define CONSOLE_CRIT_TX_STRING(string)
#define CONSOLE_CRIT_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_ERR
#undef CONSOLE_ERR_TX_CHAR
#undef CONSOLE_ERR_INLINE_TX_CHAR
#undef CONSOLE_ERR_TX_HEX8
#undef CONSOLE_ERR_INLINE_TX_HEX8
#undef CONSOLE_ERR_TX_HEX32
#undef CONSOLE_ERR_INLINE_TX_HEX32
#undef CONSOLE_ERR_TX_STRING
#undef CONSOLE_ERR_INLINE_TX_STRING
#define CONSOLE_ERR_TX_CHAR(byte)
#define CONSOLE_ERR_INLINE_TX_CHAR(byte)
#define CONSOLE_ERR_TX_HEX8(byte)
#define CONSOLE_ERR_INLINE_TX_HEX8(byte)
#define CONSOLE_ERR_TX_HEX32(lword)
#define CONSOLE_ERR_INLINE_TX_HEX32(lword)
#define CONSOLE_ERR_TX_STRING(string)
#define CONSOLE_ERR_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_WARNING
#undef CONSOLE_WARNING_TX_CHAR
#undef CONSOLE_WARNING_INLINE_TX_CHAR
#undef CONSOLE_WARNING_TX_HEX8
#undef CONSOLE_WARNING_INLINE_TX_HEX8
#undef CONSOLE_WARNING_TX_HEX32
#undef CONSOLE_WARNING_INLINE_TX_HEX32
#undef CONSOLE_WARNING_TX_STRING
#undef CONSOLE_WARNING_INLINE_TX_STRING
#define CONSOLE_WARNING_TX_CHAR(byte)
#define CONSOLE_WARNING_INLINE_TX_CHAR(byte)
#define CONSOLE_WARNING_TX_HEX8(byte)
#define CONSOLE_WARNING_INLINE_TX_HEX8(byte)
#define CONSOLE_WARNING_TX_HEX32(lword)
#define CONSOLE_WARNING_INLINE_TX_HEX32(lword)
#define CONSOLE_WARNING_TX_STRING(string)
#define CONSOLE_WARNING_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
#undef CONSOLE_NOTICE_TX_CHAR
#undef CONSOLE_NOTICE_INLINE_TX_CHAR
#undef CONSOLE_NOTICE_TX_HEX8
#undef CONSOLE_NOTICE_INLINE_TX_HEX8
#undef CONSOLE_NOTICE_TX_HEX32
#undef CONSOLE_NOTICE_INLINE_TX_HEX32
#undef CONSOLE_NOTICE_TX_STRING
#undef CONSOLE_NOTICE_INLINE_TX_STRING
#define CONSOLE_NOTICE_TX_CHAR(byte)
#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte)
#define CONSOLE_NOTICE_TX_HEX8(byte)
#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte)
#define CONSOLE_NOTICE_TX_HEX32(lword)
#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword)
#define CONSOLE_NOTICE_TX_STRING(string)
#define CONSOLE_NOTICE_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_INFO
#undef CONSOLE_INFO_TX_CHAR
#undef CONSOLE_INFO_INLINE_TX_CHAR
#undef CONSOLE_INFO_TX_HEX8
#undef CONSOLE_INFO_INLINE_TX_HEX8
#undef CONSOLE_INFO_TX_HEX32
#undef CONSOLE_INFO_INLINE_TX_HEX32
#undef CONSOLE_INFO_TX_STRING
#undef CONSOLE_INFO_INLINE_TX_STRING
#define CONSOLE_INFO_TX_CHAR(byte)
#define CONSOLE_INFO_INLINE_TX_CHAR(byte)
#define CONSOLE_INFO_TX_HEX8(byte)
#define CONSOLE_INFO_INLINE_TX_HEX8(byte)
#define CONSOLE_INFO_TX_HEX32(lword)
#define CONSOLE_INFO_INLINE_TX_HEX32(lword)
#define CONSOLE_INFO_TX_STRING(string)
#define CONSOLE_INFO_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
#undef CONSOLE_DEBUG_TX_CHAR
#undef CONSOLE_DEBUG_INLINE_TX_CHAR
#undef CONSOLE_DEBUG_TX_HEX8
#undef CONSOLE_DEBUG_INLINE_TX_HEX8
#undef CONSOLE_DEBUG_TX_HEX32
#undef CONSOLE_DEBUG_INLINE_TX_HEX32
#undef CONSOLE_DEBUG_TX_STRING
#undef CONSOLE_DEBUG_INLINE_TX_STRING
#define CONSOLE_DEBUG_TX_CHAR(byte)
#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte)
#define CONSOLE_DEBUG_TX_HEX8(byte)
#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte)
#define CONSOLE_DEBUG_TX_HEX32(lword)
#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword)
#define CONSOLE_DEBUG_TX_STRING(string)
#define CONSOLE_DEBUG_INLINE_TX_STRING(string)
#endif
#if ASM_CONSOLE_LOGLEVEL <= BIOS_SPEW
#undef CONSOLE_SPEW_TX_CHAR
#undef CONSOLE_SPEW_INLINE_TX_CHAR
#undef CONSOLE_SPEW_TX_HEX8
#undef CONSOLE_SPEW_INLINE_TX_HEX8
#undef CONSOLE_SPEW_TX_HEX32
#undef CONSOLE_SPEW_INLINE_TX_HEX32
#undef CONSOLE_SPEW_TX_STRING
#undef CONSOLE_SPEW_INLINE_TX_STRING
#define CONSOLE_SPEW_TX_CHAR(byte)
#define CONSOLE_SPEW_INLINE_TX_CHAR(byte)
#define CONSOLE_SPEW_TX_HEX8(byte)
#define CONSOLE_SPEW_INLINE_TX_HEX8(byte)
#define CONSOLE_SPEW_TX_HEX32(lword)
#define CONSOLE_SPEW_INLINE_TX_HEX32(lword)
#define CONSOLE_SPEW_TX_STRING(string)
#define CONSOLE_SPEW_INLINE_TX_STRING(string)
#endif
/* uses: esp, ax, dx */
console_tx_al:
__CONSOLE_INLINE_TX_AL
RETSP
/* uses: esp, ax, edx */
console_tx_hex8:
movb %al, %dl
shll $16, %edx
shr $4, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
shrl $16, %edx
movb %dl, %al
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
RETSP
/* uses: esp, ebx, eax, dx */
console_tx_hex32:
mov %eax, %ebx
shr $28, %eax
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
shr $24, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
shr $20, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
shr $16, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
shr $12, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
shr $8, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
shr $4, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
mov %ebx, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
__CONSOLE_INLINE_TX_AL
RETSP
/* Uses esp, ebx, ax, dx */
console_tx_string:
mov (%ebx), %al
inc %ebx
cmp $0, %al
jne 9f
RETSP
9:
__CONSOLE_INLINE_TX_AL
jmp console_tx_string
console0:
CONSOLE_INFO_TX_STRING($console_test)

61
src/arch/i386/lib/cpu_reset.inc
View file

@ -1,30 +1,54 @@
jmp cpu_reset_out
#include <cpu/p6/mtrr.h>
#include <cpu/p6/apic.h>
#include <loglevel.h>
#ifdef DEBUG
.section ".rodata"
#if ASM_CONSOLE_LOGLEVEL >= BIOS_DEBUG
cpu_reset_str: .string "cpu_reset\r\n";
cpu_apic_str: .string "apic: ";
cpu_size_set_str: .string "cpu memory size set\r\n";
#endif
.text
__cpu_reset:
#ifdef DEBUG
TTYS0_TX_STRING($cpu_reset_str);
#endif /* DEBUG */
CONSOLE_DEBUG_TX_STRING($cpu_reset_str)
#ifdef SMP
/* Enable the local apic, and map it where we expext it */
movl $APIC_BASE_MSR, %ecx
rdmsr
orl $APIC_BASE_MSR_ENABLE, %eax
andl $(~APIC_BASE_MSR_ADDR_MASK), %eax
orl $APIC_DEFAULT_BASE, %eax
/* xorl %edx, %edx */
wrmsr
/* Get the apic_id */
movl (APIC_ID + APIC_DEFAULT_BASE), %edi
shrl $24, %edi
CONSOLE_DEBUG_TX_STRING($cpu_apic_str)
CONSOLE_DEBUG_TX_HEX32(%edi)
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
#endif
CALLSP(set_memory_size)
#ifdef DEBUG
TTYS0_TX_STRING($cpu_size_set_str);
#endif /* DEBUG */
CONSOLE_DEBUG_TX_STRING($cpu_size_set_str);
#ifdef SMP
/* Test to see if we are the boot strap processor.
* If so the boot must be complete.
*/
movl $0x1b, %ecx
movl $APIC_BASE_MSR, %ecx
rdmsr
testl $0x100, %eax
testl $APIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
jnz __reboot
/* Fixed mtrrs are enabled by the C code so if they
@ -35,12 +59,23 @@ __cpu_reset:
rdmsr
testl $0x400, %eax
jnz __reboot
/* Get the apic_id */
movl (APIC_ID + APIC_DEFAULT_BASE), %edi
shrl $24, %edi
/* Get the cpu index (MAX_CPUS on error) */
movl $-4, %ebx
1: addl $4, %ebx
cmpl $(MAX_CPUS << 2), %ebx
je 2
cmpl %edi, EXT(initial_apicid)(%ebx)
jne 1b
2: shrl $2, %ebx
/* set the stack pointer */
movl $_estack, %esp
movl $APIC_DEFAULT_BASE, %edi
movl APIC_ID(%edi), %eax
shrl $24, %eax
movl %ebx, %eax
movl $STACK_SIZE, %ebx
mull %ebx
subl %eax, %esp
@ -54,3 +89,5 @@ __reboot:
jmp __main
cpu_reset_out:

74
src/arch/i386/lib/hardwaremain.c
View file

@ -59,14 +59,25 @@ static char rcsid[] = "$Id$";
#include <arch/smp/mpspec.h>
static int cpu_initialize(unsigned long totalram)
/* The processor map.
* Now that SMP is in linuxbios, and Linux counts on us
* giving accurate information about processors, we need a map
* of what processors are out there. This could be a bit mask,
* but we will be optimistic and hope we someday run on
* REALLY BIG SMPs. Also we may need more than one bit of
* info per processor at some point. I hope we don't need
* anything more complex than an int.
*/
static unsigned long processor_map[MAX_CPUS];
static unsigned long cpu_initialize(unsigned long totalram)
{
/* Because we busy wait at the printk spinlock.
* It is important to keep the number of printed messages
* from secondary cpus to a minimum, when debugging is
* disabled.
*/
int processor_id = this_processors_id();
unsigned long processor_id = this_processors_id();
printk_notice("Initializing CPU #%d\n", processor_id);
/* some cpus need a fixup done. This is the hook for doing that. */
@ -107,20 +118,24 @@ static atomic_t active_cpus = ATOMIC_INIT(1);
void secondary_cpu_init(void)
{
unsigned long totalram;
int processor_id;
unsigned long id;
int index;
printk_spew(__FUNCTION__ "\n");
atomic_inc(&active_cpus);
printk_debug(__FUNCTION__ "\n");
totalram = get_ramsize();
processor_id = cpu_initialize(totalram);
id = cpu_initialize(totalram);
index = processor_index(id);
printk_debug(__FUNCTION__ " %d/%u\n", index, id);
processor_map[index] = CPU_ENABLED;
atomic_dec(&active_cpus);
printk_spew(__FUNCTION__ " id is %d\n", processor_id);
stop_cpu(processor_id);
stop_cpu(id);
}
static void wait_for_other_cpus(void)
{
int old_active_count, active_count;
int i;
old_active_count = 1;
active_count = atomic_read(&active_cpus);
while(active_count > 1) {
@ -130,6 +145,13 @@ static void wait_for_other_cpus(void)
}
active_count = atomic_read(&active_cpus);
}
for(i = 0; i < MAX_CPUS; i++) {
if (!(processor_map[i] & CPU_ENABLED)) {
printk_err("CPU %d/%u did not initialize!\n",
i, initial_apicid);
}
}
printk_debug("All AP CPUs stopped\n");
}
#else /* SMP */
#define wait_for_other_cpus() do {} while(0)
@ -137,23 +159,16 @@ static void wait_for_other_cpus(void)
void hardwaremain(int boot_complete)
{
// The processor map.
// Now that SMP is in linuxbios, and Linux counts on us
// giving accurate information about processors, we need a map
// of what processors are out there. This could be a bit mask,
// but we will be optimistic and hope we someday run on
// REALLY BIG SMPs. Also we may need more than one bit of
// info per processor at some point. I hope we don't need
// anything more complex than an int.
unsigned long processor_map[MAX_CPUS];
// Processor ID of the BOOT cpu (i.e. the one running this code
int boot_cpu;
/* Processor ID of the BOOT cpu (i.e. the one running this code) */
unsigned long boot_cpu;
int boot_index;
// Comment: the NEW_SUPERIO architecture is actually pretty good.
// I think we need to move to the same sort of architecture for
// everything: A config file generated sequence of calls
// for initializing all the chips. We stick with this
// for now -- rgm.
/* Comment: the NEW_SUPERIO architecture is actually pretty good.
* I think we need to move to the same sort of architecture for
* everything: A config file generated sequence of calls
* for initializing all the chips. We stick with this
* for now -- rgm.
*/
#ifdef USE_NEW_SUPERIO_INTERFACE
extern struct superio *all_superio;
extern int nsuperio;
@ -204,13 +219,16 @@ void hardwaremain(int boot_complete)
/* Fully initialize the cpu before configuring the bus */
boot_cpu = cpu_initialize(totalram);
boot_index = processor_index(boot_cpu);
printk_spew("BOOT CPU is %d\n", boot_cpu);
processor_map[boot_cpu] = CPU_BOOTPROCESSOR|CPU_ENABLED;
processor_map[boot_index] = CPU_BOOTPROCESSOR|CPU_ENABLED;
/* Now start the other cpus initializing
* The sooner they start the sooner they stop.
*/
post_code(0x75);
startup_other_cpus(processor_map);
post_code(0x77);
// Now do the real bus
// we round the total ram up a lot for thing like the SISFB, which
@ -248,10 +266,6 @@ void hardwaremain(int boot_complete)
pci_zero_irq_settings();
/* copy the smp block to address 0 */
write_smp_table((void *)16, processor_map);
post_code(0x96);
check_pirq_routing_table();
copy_pirq_routing_table();
@ -271,6 +285,10 @@ void hardwaremain(int boot_complete)
/* make certain we are the only cpu running in linuxBIOS */
wait_for_other_cpus();
/* copy the smp block to address 0 */
post_code(0x96);
write_smp_table((void *)16, processor_map);
#ifdef LINUXBIOS
printk_info("Jumping to linuxbiosmain()...\n");
// we could go to argc, argv, for main but it seems like overkill.

3
src/arch/i386/smp/mpspec.c
View file

@ -105,7 +105,8 @@ void smp_write_processors(struct mp_config_table *mc,
cpu_features = eax;
cpu_feature_flags = edx;
for(i = 0; i < MAX_CPUS; i++) {
smp_write_processor(mc, i, apic_version,
unsigned long cpu_apicid = initial_apicid[i];
smp_write_processor(mc, cpu_apicid, apic_version,
processor_map[i],
cpu_features, cpu_feature_flags
);

50
src/arch/i386/smp/start_stop.c
View file

@ -2,6 +2,9 @@
#include <arch/smp/mpspec.h>
#include <cpu/p6/apic.h>
#include <delay.h>
#include <string.h>
static inline void hlt(void)
{
@ -9,12 +12,23 @@ static inline void hlt(void)
return;
}
int this_processors_id(void)
unsigned long this_processors_id(void)
{
return apic_read(APIC_ID) >> 24;
}
void stop_cpu(int apicid)
int processor_index(unsigned long apicid)
{
int i;
for(i = 0; i < MAX_CPUS; i++) {
if (initial_apicid[i] == apicid) {
return i;
}
}
return -1;
}
void stop_cpu(unsigned long apicid)
{
int timeout;
unsigned long send_status;
@ -32,7 +46,7 @@ void stop_cpu(int apicid)
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_spew("timed out\n");
printk_err("timed out\n");
}
mdelay(10);
@ -49,7 +63,7 @@ void stop_cpu(int apicid)
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_debug("timed out\n");
printk_err("timed out\n");
}
while(1) {
@ -61,11 +75,13 @@ void stop_cpu(int apicid)
// This is a lot more paranoid now, since Linux can NOT handle
// being told there is a CPU when none exists. So any errors
// will return 0, meaning no CPU.
int start_cpu(int apicid)
int start_cpu(unsigned long apicid)
{
int timeout;
unsigned long send_status, accept_status, start_eip;
int j, num_starts, maxlvt;
extern char _start[], _estart[];
/*
* Starting actual IPI sequence...
*/
@ -102,7 +118,6 @@ int start_cpu(int apicid)
}
return 0;
}
mdelay(10);
printk_spew("Deasserting INIT.\n");
@ -127,8 +142,12 @@ int start_cpu(int apicid)
return 0;
}
/* FIXME start_eip should be more flexible! */
start_eip = 0xf0000;
start_eip = 0x90000 + (((unsigned long)_start) & 0xf000);
if ((((unsigned long)_start) & 0xfff) != 0) {
printk_err("_start is not 4K aligned!\n");
return 0;
}
memcpy((void *)start_eip, _start, _estart - _start);
printk_spew("start eip=0x%08lx\n", start_eip);
num_starts = 2;
@ -199,17 +218,22 @@ int start_cpu(int apicid)
return 1;
}
void startup_other_cpus(unsigned long *processor_map)
{
int apicid = this_processors_id();
unsigned long apicid = this_processors_id();
int i;
/* Assume the cpus are densly packed by apicid */
for(i = 0; i < MAX_CPUS; i++) {
if (i == apicid ) {
unsigned long cpu_apicid = initial_apicid[i];
if (cpu_apicid == apicid ) {
continue;
}
if (start_cpu(i))
processor_map[i] = CPU_ENABLED;
if (!start_cpu(cpu_apicid)) {
/* Put an error in processor_map[i]? */
printk_err("CPU %d/%u would not start!\n",
i, cpu_apicid);
}
}
}

73
src/cpu/i386/entry16.inc
View file

@ -25,44 +25,14 @@ it with the version available from LANL.
* protected mode.
*/
#include <arch/cache_ram.h>
.text
.code16
.globl EXT(_start)
.type EXT(_start), @function
/// We have a relative jump here to around the GDT.
EXT(_start): jmp _realstart
/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
* at 0x18; these are Linux-compatible.
*/
#ifndef CACHE_RAM_BASE
#define CACHE_RAM_BASE 0
#endif
/** GDT. we have modified this from the original freebios to make it
* compatible with linux. This puts text at seg 0x10 and data at 0x18
*/
.align 4
.globl EXT(gdtptr)
EXT(gdtptr):
.word 4*8-1
.long gdt /* we know the offset */
gdt:
.word 0x0000, 0x0000 /* dummy */
.byte 0x00, 0x00, 0x00, 0x00
.word 0xffff, (CACHE_RAM_BASE & 0xffff) /* flat offset data segment */
.byte ((CACHE_RAM_BASE >> 16)& 0xff), 0x93, 0xcf, ((CACHE_RAM_BASE >> 24) & 0xff)
.word 0xffff, 0x0000 /* flat code segment */
.byte 0x00, 0x9b, 0xcf, 0x00
.word 0xffff, 0x0000 /* flat data segment */
.byte 0x00, 0x93, 0xcf, 0x00
_realstart:
EXT(_start):
cli
/* thanks to kmliu@sis.tw.com for this TBL fix ... */
@ -115,7 +85,40 @@ _realstart:
movl %eax, %cr0
/* Now that we are in protected mode jump to a 32 bit code segment. */
data32 ljmp $0x10, $.Lprotected
data32 ljmp $0x10, $_protected_start
/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
* at 0x18; these are Linux-compatible.
*/
/** GDT. we have modified this from the original freebios to make it
* compatible with linux. This puts text at seg 0x10 and data at 0x18
*/
.align 4
.globl EXT(gdtptr)
EXT(gdtptr):
.word 4*8-1
.long gdt /* we know the offset */
.globl EXT(_estart)
EXT(_estart):
gdt:
.word 0x0000, 0x0000 /* dummy */
.byte 0x00, 0x00, 0x00, 0x00
.word 0xffff, (CACHE_RAM_SEG_BASE & 0xffff) /* flat offset data segment */
.byte ((CACHE_RAM_SEG_BASE >> 16)& 0xff), 0x93, 0xcf
.byte ((CACHE_RAM_SEG_BASE >> 24) & 0xff)
.word 0xffff, 0x0000 /* flat code segment */
.byte 0x00, 0x9b, 0xcf, 0x00
.word 0xffff, 0x0000 /* flat data segment */
.byte 0x00, 0x93, 0xcf, 0x00
/*
* When we come here we are in protected mode. We expand
@ -129,7 +132,7 @@ _realstart:
* cache will be reloaded.
*/
.align 4
.Lprotected:
_protected_start:
.code32
intel_chip_post_macro(0x10) /* post 10 */

9
src/cpu/i786/cache_ram_init.inc
View file

@ -25,12 +25,17 @@
andl $0x9fffffff, %eax
movl %eax, %cr0
/* Force cache ram area into cache */
/* Force cache ram area into cache
* Note: Some versions of the P4 don't allocate a cache
* line on write immediately after a mtrr change, so
* we make certain we read the address before we write
* to it.
*/
movl $CACHE_RAM_BASE, %esi
movl $(CACHE_RAM_BASE + CACHE_RAM_SIZE), %edi
1: movl (%esi), %eax
addl $4, %esi
movl %eax, (%esi)
movl %eax, -4(%esi)
cmpl %esi, %edi
jnz 1b

6
src/cpu/i786/cache_ram_start.inc
View file

@ -1,7 +1,9 @@
#include <arch/cache_ram.h>
/* copy data segment from FLASH ROM to CACHE */
movl $(EXT(_ldata) - CACHE_RAM_BASE), %esi
movl $(EXT(_ldata) - CACHE_RAM_SEG_BASE), %esi
movl $EXT(_data), %edi
movl $(EXT(_eldata) - CACHE_RAM_BASE), %ecx
movl $(EXT(_eldata) - CACHE_RAM_SEG_BASE), %ecx
subl %esi, %ecx
jz 1f /* should not happen */
rep

10
src/cpu/p6/mtrr.c
View file

@ -286,10 +286,12 @@ void setup_mtrrs(unsigned long ramsizeK)
MTRR_TYPE_WRBACK);
rambase += ramsizeK;
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: UC\n",
reg, rambase >> 10, range_uc >> 10);
intel_set_var_mtrr(reg++, rambase * 1024, range_uc * 1024,
MTRR_TYPE_UNCACHABLE);
if (range_uc) {
printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type: UC\n",
reg, rambase >> 10, range_uc >> 10);
intel_set_var_mtrr(reg++, rambase * 1024, range_uc * 1024,
MTRR_TYPE_UNCACHABLE);
}
ramsizeK = 0; /* effectivly a break */
} else {
range_wb >>= 1;

2
src/include/cpu/cpufixup.h
View file

@ -7,6 +7,8 @@
#ifdef CPU_FIXUP
# if defined(k7)
# define cpufixup(totalram) k7_cpufixup(totalram)
# elif defined(i786)
# define cpufixup(totalram) p6_cpufixup(totalram)
# elif defined(i686)
# define cpufixup(totalram) p6_cpufixup(totalram)
# endif

2
src/include/cpu/l2_cache.h
View file

@ -4,7 +4,7 @@
#include <cpu/p6/l2_cache.h>
#ifdef CONFIGURE_L2_CACHE
# if defined(i686)
# if defined(i686) && !defined(i786)
# define configure_l2_cache() p6_configure_l2_cache()
# endif
#else

13
src/include/cpu/p6/apic.h
View file

@ -139,7 +139,7 @@ static inline void apic_wait_icr_idle(void)
#ifdef CONFIG_X86_GOOD_APIC
# define FORCE_READ_AROUND_WRITE 0
# define apic_read_around(x)
# define apic_read_around(x) apic_read(x)
# define apic_write_around(x,y) apic_write((x),(y))
#else
# define FORCE_READ_AROUND_WRITE 1
@ -147,10 +147,11 @@ static inline void apic_wait_icr_idle(void)
# define apic_write_around(x,y) apic_write_atomic((x),(y))
#endif
static inline unsigned long apic_remote_read(int apicid, int reg)
static inline int apic_remote_read(int apicid, int reg, unsigned long *pvalue)
{
int timeout;
unsigned long status, result;
unsigned long status;
int result;
apic_wait_icr_idle();
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write_around(APIC_ICR, APIC_DM_REMRD | (reg >> 4));
@ -164,10 +165,8 @@ static inline unsigned long apic_remote_read(int apicid, int reg)
result = -1;
if (status == APIC_ICR_RR_VALID) {
result = apic_read(APIC_RRR);
}
else {
printk_err("remote apic read failed\n");
*pvalue = apic_read(APIC_RRR);
result = 0;
}
return result;
}

26
src/include/loglevel.h Normal file
View file

@ -0,0 +1,26 @@
#ifndef LOGLEVEL_H
#define LOGLEVEL_H
/* Safe for inclusion in assembly */
#ifndef MAXIMUM_CONSOLE_LOGLEVEL
#define MAXIMUM_CONSOLE_LOGLEVEL 8
#endif
#if (DEFAULT_CONSOLE_LOGLEVEL <= MAXIMUM_CONSOLE_LOGLEVEL)
#define ASM_CONSOLE_LOGLEVEL DEFAULT_CONSOLE_LOGLEVEL
#else
#define ASM_CONSOLE_LOGLEVEL MAXIMUM_CONSOLE_LOGLEVEL
#endif
#define BIOS_EMERG 0 /* system is unusable */
#define BIOS_ALERT 1 /* action must be taken immediately */
#define BIOS_CRIT 2 /* critical conditions */
#define BIOS_ERR 3 /* error conditions */
#define BIOS_WARNING 4 /* warning conditions */
#define BIOS_NOTICE 5 /* normal but significant condition */
#define BIOS_INFO 6 /* informational */
#define BIOS_DEBUG 7 /* debug-level messages */
#define BIOS_SPEW 8 /* Way too many details */
#endif /* LOGLEVEL_H */

2
src/include/pci_ids.h
View file

@ -262,6 +262,8 @@
#define PCI_DEVICE_ID_AMD_SCSI 0x2020
#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
#define PCI_DEVICE_ID_AMD_761_0 0x700E
#define PCI_DEVICE_ID_AMD_761_1 0x700F
#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400
#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401
#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403

32
src/include/printk.h
View file

@ -1,19 +1,7 @@
#ifndef PRINTK_H
#define PRINTK_H
#ifndef MAXIMUM_CONSOLE_LOGLEVEL
#define MAXIMUM_CONSOLE_LOGLEVEL 8
#endif
#define BIOS_EMERG 0 /* system is unusable */
#define BIOS_ALERT 1 /* action must be taken immediately */
#define BIOS_CRIT 2 /* critical conditions */
#define BIOS_ERR 3 /* error conditions */
#define BIOS_WARNING 4 /* warning conditions */
#define BIOS_NOTICE 5 /* normal but significant condition */
#define BIOS_INFO 6 /* informational */
#define BIOS_DEBUG 7 /* debug-level messages */
#define BIOS_SPEW 8 /* Way too many details */
#include <loglevel.h>
extern int console_loglevel;
int do_printk(int msg_level, const char *fmt, ...);
@ -28,39 +16,39 @@ int do_printk(int msg_level, const char *fmt, ...);
#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
#define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg)
#if MAXIMUM_CONSOLE_LOGLEVEL <= 0
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
#undef printk_emerg
#define printk_emerg(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 1
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
#undef printk_alert
#define printk_alart(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 2
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
#undef printk_crit
#define printk_crit(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 3
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
#undef printk_err
#define printk_err(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 4
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
#undef printk_warning
#define printk_warning(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 5
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
#undef printk_notice
#define printk_notice(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 6
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
#undef printk_info
#define printk_info(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 7
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
#undef printk_debug
#define printk_debug(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= 8
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
#undef printk_spew
#define printk_spew(fmt, arg...) do {} while(0)
#endif

7
src/include/smp/start_stop.h
View file

@ -3,9 +3,10 @@
#ifdef SMP
#include <smp/atomic.h>
int this_processors_id(void);
void stop_cpu(int processor_id);
int start_cpu(int processor_id);
unsigned long this_processors_id(void);
int processor_index(unsigned long processor_id);
void stop_cpu(unsigned long processor_id);
int start_cpu(unsigned long processor_id);
void startup_other_cpus(unsigned long *processor_map);
#else
#define this_processors_id() 0

5
src/include/southbridge/intel/82801.h Normal file
View file

@ -0,0 +1,5 @@
void ich2_enable_serial_irqs(void);
void ich2_lpc_route_dma(unsigned char mask);
void ich2_enable_ioapic(void);
void ich2_enable_ide(int enable_a, int enable_b);

38
src/mainboard/asus/a7m/Config Normal file
View file

@ -0,0 +1,38 @@
arch i386
mainboardinit northbridge/amd/amd76x/reset_test.inc
mainboardinit cpu/k7/earlymtrr.inc
mainboardinit northbridge/amd/amd76x/mpinit.inc
mainboardinit superio/via/vt82c686/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit mainboard/asus/a7m/smbus.inc
mainboardinit sdram/generic_dump_spd.inc
mainboardinit mainboard/asus/a7m/mainboard_raminit.inc
northbridge amd/amd76x
southbridge via/vt82c686
option RAMTEST=1
option NO_KEYBOARD
option ENABLE_FIXED_AND_VARIABLE_MTRRS
#option HAVE_MP_TABLE=1
#option FINAL_MAINBOARD_FIXUP
object mainboard.o
#object mptable.o
#keyboard pc80
dir ../../../pc80
# FIXME are the SMBUS DIMM locations documented anywhere?
option SMBUS_MEM_DEVICE_START=(0xa << 3)
option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3)
option SMBUS_MEM_DEVICE_INC=1
#option SIO_BASE=0x2e
#option IOAPIC=1
option USE_AMD_NDA_CODE=1
option SUPERIO_DEVFN=0x20
option PM_DEVFN=0x2400
cpu p5
cpu p6
cpu k7

28
src/mainboard/asus/a7m/do_ramtest.inc Normal file
View file

@ -0,0 +1,28 @@
#if 0
movl $0x000f0000, %eax
movl $0x000f1000, %ebx
CALLSP(ramtest)
#endif
#if 1
movl $0x00100000, %eax
movl $0x00180000, %ebx
CALLSP(ramtest)
xorl %eax, %eax
movl $0x00080000, %ebx
CALLSP(ramtest)
#endif
#if 1
xorl %eax, %eax
movl $0x00001000, %ebx
CALLSP(ramtest)
#endif
#if 0
movl $0xffe00000, %eax
movl $0xfff00000, %ebx
CALLSP(ramtest)
#endif

173
src/mainboard/asus/a7m/mainboard.c Normal file
View file

@ -0,0 +1,173 @@
#include <pci_ids.h>
#include <pci.h>
#include <arch/io.h>
#include <printk.h>
#include <arch/pirq_routing.h>
#define CHECKSUM 0x8d
static void pci_routing_fixup(void)
{
struct pci_dev *dev;
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev != NULL) {
/* initialize PCI interupts */
pci_write_config_byte(dev, 0x51, 0x76);
pci_write_config_byte(dev, 0x55, 0xc0);
pci_write_config_byte(dev, 0x56, 0x0a);
pci_write_config_byte(dev, 0x57, 0xc0);
}
}
static void a7m_northbridge_fixup(void)
{
struct pci_dev *dev;
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_761_1, 0);
if (dev != NULL) {
/* load addresses and limits */
pci_write_config_byte(dev, 0x1c, 0xd1);
pci_write_config_byte(dev, 0x1d, 0xd1);
pci_write_config_byte(dev, 0x20, 0x80);
pci_write_config_byte(dev, 0x21, 0xf5);
pci_write_config_byte(dev, 0x22, 0x50);
pci_write_config_byte(dev, 0x23, 0xf7);
pci_write_config_byte(dev, 0x24, 0x70);
pci_write_config_byte(dev, 0x25, 0xf7);
pci_write_config_byte(dev, 0x26, 0x70);
pci_write_config_byte(dev, 0x27, 0xf7);
}
}
static void pci_functions_fixup(void)
{
struct pci_dev *dev;
struct pci_dev dev_cpy;
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev != NULL) {
printk_debug("PCI function 0 found\n");
/* initialize PCI misc */
pci_write_config_byte(dev, 0x70, 0x43);
pci_write_config_byte(dev, 0x71, 0x10);
pci_write_config_byte(dev, 0x72, 0x40);
pci_write_config_byte(dev, 0x73, 0x80);
pci_write_config_byte(dev, 0x7a, 0x60);
memcpy(&dev_cpy,dev,sizeof(dev_cpy));
dev=&dev_cpy;
dev->devfn|=1; /* increment to function 1 */
}
else
printk_debug("PCI function 1 Not found\n");
}
static void pci_eth0_fixup(void)
{
struct pci_dev *dev;
dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557, 0);
if (dev != NULL) {
/* initialize PCI Intel ethernet controler interupt line */
pci_write_config_byte(dev, 0x3c, 0x0c);
pci_write_config_byte(dev, 0x3d, 0x01);
/* The following were added ???? */
pci_write_config_byte(dev, 0x04, 0x07);
pci_write_config_byte(dev, 0x0c, 0x08);
pci_write_config_byte(dev, 0x0d, 0x20);
}
else
printk_debug("PCI eth0 Not found\n");
}
static void lpc_generic_range_enable(void)
{
struct pci_dev *dev;
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410,0);
if (dev != NULL) {
/* Send io addres 0x0c00 the LPC bus */
pci_write_config_dword(dev, 0x58, 0x0c01);
}
}
const struct irq_routing_table via_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*9, /* there can be total 9 devices on the bus */
0x00, /* Bus 0 */
0x20, /* Device 1, Function 0 */
0x0000, /* reserve IRQ for PCI */
0x1106, /* VIA Technologies */
0x0586, /* VT82C686 ISA Bridge */
0x00, /* u32 miniport_data - "crap" */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, 0x20, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x05, 0x1eb8}}, 0x00, 0x00},
{0x00, 0x60, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x05, 0x1eb8}}, 0x01, 0x00},
{0x00, 0x58, {{0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x05, 0x1eb8}, {0x01, 0x1eb8}}, 0x02, 0x00},
{0x00, 0x50, {{0x03, 0x1eb8}, {0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}}, 0x03, 0x00},
{0x00, 0x48, {{0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x04, 0x00},
{0x00, 0x68, {{0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}}, 0x05, 0x00},
{0x00, 0x38, {{0x03, 0x1eb8}, {0x05, 0x1eb8}, {0x01, 0x1eb8}, {0x02, 0x1eb8}}, 0x00, 0x00},
{0x00, 0x28, {{0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x05, 0x1eb8}, {0x01, 0x1eb8}}, 0x00, 0x00},
{0x01, 0x28, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x05, 0x1eb8}}, 0x06, 0x00},
}
};
void load_irq_routing_table(void)
{
unsigned char *bios_ram;
int cnt;
unsigned char *irq_table;
printk_debug("Loading irq routing table\n");
irq_table=(unsigned char *)&via_irq_routing_table;
bios_ram=(unsigned char *)0x0f0000;
for(cnt=0;cnt<176;cnt++)
bios_ram[cnt]=irq_table[cnt];
printk_debug("irq routing table loaded\n");
return;
}
static unsigned int pci_table[12]=
{0x80000000,0x80000800,0x80002000,0x80002100,0x80002200,
0x80002300,0x80002400,0x80002800,0x80004800,0x80012800,0,0};
void pci_dump(void)
{
unsigned int addr;
int cntb,cnta;
unsigned char chr;
printk_info("Printing pci table\n");
for(cnta=0;cnta<10;cnta++)
{
for(cntb=0;cntb<256;cntb++)
{
if((cntb%16)==0)
printk_info("\n");
addr=pci_table[cnta]+cntb;
chr=intel_conf_readb(addr);
printk_info("%2.2x ",chr);
}
printk_info("\n\n");
}
printk_info("pci table done\n");
return;
}
void mainboard_fixup(void)
{
pci_routing_fixup();
pci_eth0_fixup();
keyboard_on();
a7m_northbridge_fixup();
southbridge_fixup();
pci_functions_fixup();
load_irq_routing_table();
// rtc_init();
// pci_dump();
}

140
src/mainboard/asus/a7m/mainboard_raminit.inc Normal file
View file

@ -0,0 +1,140 @@
jmp mainboard_raminit_out
#define DEFAULT_RAM_TRACE_SETTINGS 0
#define USE_ECC_SDRAM 1
/*
* Routine: spd_to_dimm_side0
* Arguments: %bl SMBUS_MEM_DEVICE
*
* Results: %edx DIMM register index
*
* Used: %ebx, %edx, %esp
* Trashed: %eflags
* Preserved: %eax, %ebx, %ecx, %esi, %edi, %ebp
*
* Effects: Dimms are not necessarily in the same order on the smbus
* as they are in chipset register indexes. This function
* maps the SMBUS device id to the logical index in
* the chipset, that is used to refer to a particular dimm.
*/
spd_to_dimm_side0:
movl %ebx, %edx
andl $0xff, %edx
subl $(SMBUS_MEM_DEVICE_START), %edx
/* 0 -> 0 */
cmpl $0, %edx
jne 1f
movl $0, %edx
RETSP
/* 1 -> 2 */
1: cmpl $1, %edx
jne 1f
movl $2, %edx
RETSP
/* 2 -> 4 */
1: cmpl $2, %edx
jne 1f
movl $4, %edx
RETSP
/* 3 -> 6 */
1: movl $6, %edx
RETSP
/*
* Routine: spd_to_dimm_side1
* Arguments: %bl SMBUS_MEM_DEVICE
*
* Results: %edx DIMM register index
*
* Used: %ebx, %edx, %esp
* Trashed: %eflags
* Preserved: %eax, %ebx, %ecx, %esi, %edi, %ebp
*
* Effects: Dimms are not necessarily in the same order on the smbus
* as they are in chipset register indexes. This function
* maps the SMBUS device id to the logical index in
* the chipset, that is used to refer to a particular dimm.
*/
spd_to_dimm_side1:
movl %ebx, %edx
andl $0xff, %edx
subl $(SMBUS_MEM_DEVICE_START), %edx
/* 0 -> 1 */
cmpl $0, %edx
jne 1f
movl $1, %edx
RETSP
/* 1 -> 3 */
1: cmpl $1, %edx
jne 1f
movl $3, %edx
RETSP
/* 2 -> 5 */
1: cmpl $2, %edx
jne 1f
movl $5, %edx
RETSP
/* 3 -> 7 */
1: movl $7, %edx
RETSP
/* Set the calibration delay. These values may need to change per mainboard
* so we put them here.
*/
sdram_software_calibration_delay:
#if DEFAULT_RAM_TRACE_SETTINGS
.byte 0x69, 0x00, 0x00, 0x6b
#else
.byte 0x69, 0x00, 0x00, 0x54
#endif
mainboard_constant_register_values:
#if DEFAULT_RAM_TRACE_SETTINGS
#else
.long 0x18c, 0x090e2d0e
.long 0x190, 0x3f0f2d0e
.long 0x194, 0x2d0e2d0e
.long 0x198, 0x2d0e2d0e
#endif
#if USE_ECC_SDRAM
.long 0x48, (3 << 14)|(2 << 10)|(0 << 8)|(0 << 4)|(0 << 0)
#else
.long 0x48, 0
#endif
mainboard_constant_register_values_end:
/*
* Routine: mainboard_verify_dram_timing
* Arguments: %edi the computed timing for the current dimm.
* Trashed: %eflags
* Results: cf clear
* %edi has a timing supported by this motherboard
* On Error:
* cf set
* %edi holds a timing not supported by this motherboard
*
* Effects: Verifies we can use the current dimm settings
* on the tyan guinness motherboard.
* Currently the only potential problem is putting
* in unregistered SDRAM.
*/
mainboard_verify_dram_timing:
testl $(1<<27), %edi
jnz mainboard_verify_dram_timing_ok
mainboard_verify_dram_timing_error:
stc
jmp mainboard_verify_dram_timing_out
mainboard_verify_dram_timing_ok:
clc
mainboard_verify_dram_timing_out:
RET_LABEL(mainboard_verify_dram_timing)
#undef DEFAULT_RAM_TRACE_SETTINGS
mainboard_raminit_out:

209
src/mainboard/asus/a7m/smbus.inc Normal file
View file

@ -0,0 +1,209 @@
/* Useful macros PCIBUS, and SMBUS functions for getting DRAM going. */
/* courtesy Eric Biederman of linuxnetworx.com */
#define CS_WRITE_BYTE(addr, byte) \
movl $addr, %eax ; \
movl $byte, %edx ; \
PCI_WRITE_CONFIG_BYTE
#define CS_WRITE_WORD(addr, word) \
movl $addr, %eax ; \
movl $word, %ecx ; \
PCI_WRITE_CONFIG_WORD
#define CS_WRITE_LONG(addr, dword) \
movl $addr, %eax ; \
movl $dword, %ecx ; \
PCI_WRITE_CONFIG_DWORD
#define DEVFN(device, function) (((device) << 3) + (function))
#ifndef CONFIG_ADDR
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
#endif
/* jump around these subrs */
jmp smbus_end
/* generic SMB routines that work for many systems. The only one that might
* not work is the enable_smbus.
* you have to define PM_FUNCTION for this to work.
*/
#define SMBUS_IO_BASE 0xf00
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
#define SMBHSTCMD 3
#define SMBHSTADD 4
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
enable_smbus:
/* put the SMBUS at port 0xf00 */
CS_WRITE_LONG(PM_DEVFN+ 0x90, SMBUS_IO_BASE|1) /* iobase addr */
CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */
CS_WRITE_WORD(PM_DEVFN + 0x4, 1) /* iospace enable */
RET_LABEL(enable_smbus)
/*
* Routine: setup_smbus
* Arguments: none
* Results: none
* Trashed: eax, edx
* Effects: The smbus is enabled
*/
setup_smbus:
xor %eax,%eax
movl $(SMBUS_IO_BASE +SMBHSTSTAT), %edx
outb %al, %dx
RET_LABEL(setup_smbus)
#define SMBUS_MEM_DEVICE_0 (0xa << 3)
#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
#define SMBUS_SPD 0
#if SMBUS_SPD
/*
* Routine: smbus_wait_until_ready
* Arguments: none
* Results: none
* Trashed: eax, edx
* Effects: Upon return the smbus is ready to accept commands
*/
smbus_wait_until_ready:
movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
1: inb %dx, %al
testb $1, %al
jnz 1b
RET_LABEL(smbus_wait_until_ready)
/*
* Routine: smbus_wait_until_done
* Arguments: none
* Results: none
* Trashed: eax, edx
* Effects: Upon return the smbus has completed it's most recent transation
*/
smbus_wait_until_done:
movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
1: inb %dx, %al
testb $1, %al
jnz 1b
2: testb $0xFE, %al
jnz 3f
inb %dx, %al
testb $0xFE, %al
jz 2b
3: RET_LABEL(smbus_wait_until_done)
#endif
/*
* Routine: smbus_read_byte
* Arguments: %esp return address
* %bl device on the smbus to read from
* %bh address on the smbus to read
*
* Results: zf clear
* byte read %eax
* On Error:
* zf set
* %eax trashed
*
* Trashed: %edx, %eax
* Effects: reads a byte off of the smbus
*/
#define SMBUS_READ_BYTE(device, address) \
movl $( (device) | ((address) << 8)), %ebx ; \
CALLSP(smbus_read_byte)
#if SMBUS_SPD
smbus_read_byte:
/* poll until the smbus is ready for commands */
CALL_LABEL(smbus_wait_until_ready)
/* clear any lingering errors, so that the transaction will run */
movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
inb %dx, %al
outb %al, %dx
/* set the device I'm talking to */
movl $(SMBUS_IO_BASE + SMBHSTADD), %edx
movb %bl /* device */, %al
shlb $1, %al
orb $1, %al
outb %al, %dx
/* set the command address... */
movl $(SMBUS_IO_BASE + SMBHSTCMD), %edx
movb %bh /* address */, %al
outb %al, %dx
/* clear the data byte */
movl $(SMBUS_IO_BASE + SMBHSTDAT0), %edx
xorl %eax, %eax
outb %al, %dx
/* start a byte read, with interrupts disabled */
movl $(SMBUS_IO_BASE + SMBHSTCTL), %edx
movl $((0x2 << 2) | (1 << 6)), %eax
outb %al, %dx
/* poll for transaction completion */
CALL_LABEL(smbus_wait_until_done)
/* read the results and see if we succeded */
movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
inb %dx, %al
testb $0x02, %al
jz 1f
movl $(SMBUS_IO_BASE + SMBHSTDAT0), %edx
inb %dx, %al
1:
RETSP
#else
/* This table and code are used because I could not get
the smbus to work, so the table below is for dimm ram
that is compatable to the Samsung M383L3313BT1-B0.
The routine below simulates an smbus read for address
0x50 and 0x51.
*/
smbus_spd_table:
.byte 0x80, 0x08, 0x07, 0x0c, 0x0a, 0x02, 0x48, 0x00
.byte 0x04, 0x75, 0x75, 0x02, 0x80, 0x08, 0x08, 0x01
.byte 0x0e, 0x04, 0x0c, 0x01, 0x02, 0x26, 0x00, 0xa0
.byte 0x75, 0x00, 0x00, 0x50, 0x3c, 0x50, 0x2d, 0x20
.byte 0x90, 0x90, 0x50, 0x50, 0x00, 0x00, 0x00, 0x00
smbus_spd_table_end:
smbus_read_byte:
/* test for a valid device */
cmpb $0x50, %bl
jz srb10;
cmpb $0x51, %bl
jnz srb_err
srb10:
/* get the index in eax */
xorl %eax, %eax
movb %bh, %al
/* load the byte from the table */
movl $smbus_spd_table, %edx
addl %eax, %edx
movb 0(%edx), %al
cmpl $smbus_spd_table_end, %edx
jb srb20
movb $0, %al
/* clear the zero flag */
srb20:
testl %edx, %edx
RETSP
srb_err:
xorl %eax, %eax
RETSP
#endif
smbus_end:
CALL_LABEL(enable_smbus)
CALL_LABEL(setup_smbus)

1
src/mainboard/asus/cua/Config
View file

@ -5,6 +5,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit northbridge/acer/m1631/chipset_init.inc
mainboardinit superio/acer/m1535/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge acer/m1631
southbridge acer/m1535

1
src/mainboard/dell/350/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/SMC/fdc37b907/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc

1
src/mainboard/gigabit/ga-6bxc/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/ITE/it8671f/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc

23
src/mainboard/gigabit/ga-6bxc/crt0.S
View file

@ -63,17 +63,16 @@ delaytest: .string "Delay test... "
#ifdef SERIAL_CONSOLE
#include <pc80/serial.inc>
#endif
#include <arch/i386/lib/console.inc>
#include <ram/ramtest.inc>
intel_chip_post_macro(0x04)
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($separator)
TTYS0_TX_STRING($greeting)
TTYS0_TX_STRING($date)
TTYS0_TX_CHAR($'\n')
#endif
CONSOLE_DEBUG_TX_STRING($separator)
CONSOLE_DEBUG_TX_STRING($greeting)
CONSOLE_DEBUG_TX_STRING($date)
CONSOLE_DEBUG_TX_CHAR($'\n')
intel_chip_post_macro(0x05)
/* initialize the RAM */
@ -128,9 +127,7 @@ delaytest: .string "Delay test... "
intel_chip_post_macro(0x30)
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($initdata)
#endif
CONSOLE_DEBUG_TX_STRING($initdata)
/*
* Copy data into RAM and clear the BSS. Since these segments
@ -165,9 +162,7 @@ delaytest: .string "Delay test... "
stosb
.Lnobss:
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($done)
#endif
CONSOLE_DEBUG_TX_STRING($done)
intel_chip_post_macro(0x3f)
/*
@ -176,9 +171,7 @@ delaytest: .string "Delay test... "
* let it do the rest.
*/
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($jumpmain)
#endif
CONSOLE_DEBUG_TX_STRING($jumpmain)
/* memory is up. Let's do the rest in C -- much easier. */
/* set new stack */

1
src/mainboard/gigabit/ga-6oxe/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/ITE/it8712f/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/815ep
southbridge intel/ich2
mainboardinit cpu/p6/earlymtrr.inc

1
src/mainboard/intel/l440bx/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/SMC/fdc37c669/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc

9
src/mainboard/intel/l440bx/crt0.S
View file

@ -29,8 +29,9 @@
#include <superio/NSC/pc87309/setup_serial.inc>
#include <pc80/serial.inc>
#include <arch/i386/lib/console.inc>
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -66,7 +67,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -78,7 +79,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -102,7 +103,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

1
src/mainboard/intel/l440gx/Config
View file

@ -9,6 +9,7 @@ mainboardinit northbridge/intel/440gx/reset_test.inc
mainboardinit superio/NSC/pc87309/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440gx
southbridge intel/piix4e

9
src/mainboard/intel/l440gx/crt0.S
View file

@ -29,8 +29,9 @@
#include <superio/NSC/pc87309/setup_serial.inc>
#include <pc80/serial.inc>
#include <arch/i386/lib/console.inc>
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -66,7 +67,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -78,7 +79,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -102,7 +103,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

8
src/mainboard/intel/l440gx/mainboard.c
View file

@ -1,11 +1,15 @@
#include <printk.h>
#include <pci.h>
#include <arch/io.h>
#include <arch/smp/mpspec.h>
#include <cpu/p5/io.h>
unsigned long initial_apicid[MAX_CPUS] =
{
0, 1
};
// this needs to be moved about a bit to northbridge.c etc.
void mainboard_fixup()
{
struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;

1
src/mainboard/irobot/proto1/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/SMC/fdc37n769/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc

1
src/mainboard/lanner/em-370/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/winbond/w83977ef/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
superio winbond/w83977ef

1
src/mainboard/leadtek/winfast6300/Config
View file

@ -4,6 +4,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/sis/950/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northsouthbridge sis/630
# superio sis/950
nsuperio sis/950 com1={1} floppy=1 lpt=1

1
src/mainboard/matsonic/ms7308e/Config
View file

@ -4,6 +4,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/sis/950/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northsouthbridge sis/630
# superio sis/950
nsuperio sis/950 com1={1} floppy=1 lpt=1

1
src/mainboard/pcchips/m754lmr/Config
View file

@ -8,6 +8,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/acer/m1535/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge acer/m1631
southbridge acer/m1535

1
src/mainboard/pcchips/m810lmr/Config
View file

@ -4,6 +4,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/sis/950/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northsouthbridge sis/730
# superio sis/950
nsuperio sis/950 com1={1} floppy=1 lpt=1

1
src/mainboard/rcn/dc1100s/Config
View file

@ -4,6 +4,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/via/vt82c686/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge via/vt694
southbridge via/vt82c686
superio via/vt82c686

1
src/mainboard/sis/540/Config
View file

@ -4,6 +4,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/sis/950/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northsouthbridge sis/540
# superio sis/950
nsuperio sis/950 com1={1} floppy=1 lpt=1

19
src/mainboard/supermicro/p4dc6/Config
View file

@ -13,11 +13,11 @@ option CACHE_RAM_SIZE=0x00010000
option USE_CACHE_RAM=1
nooption USE_DEFAULT_LAYOUT
#rambase 0xfff70000
rambase 0x00000000
rambase 0x00000800
option STACK_SIZE=0x2000
#mainboardinit northbridge/amd/amd76x/reset_test.inc
mainboardinit northbridge/intel/82860/reset_test.inc
#mainboardinit southbridge/intel/82801/definitions.inc
#mainboardinit southbridge/intel/82801/disable_watchdog.inc
@ -25,8 +25,9 @@ option STACK_SIZE=0x2000
mainboardinit cpu/i786/earlymtrr.inc
mainboardinit superio/winbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
#mainboardinit ram/ramtest.inc
#mainboardinit mainboard/supermicro/p4dc6/spin.inc
#mainboardinit northbridge/intel/82860/reset_test.inc
mainboardinit cpu/i786/cache_ram_init.inc
#mainboardinit mainboard/supermicro/p4dc6/cache_test.inc
mainboardinit cpu/i786/cache_ram_start.inc
@ -46,6 +47,7 @@ option ENABLE_FIXED_AND_VARIABLE_MTRRS
object cacheramtest.o
object mainboard.o
object mtrr_values.o
object mptable.o HAVE_MP_TABLE
object irq_tables.o HAVE_PIRQ_TABLE
#keyboard pc80
@ -56,16 +58,15 @@ option SMBUS_MEM_DEVICE_START=(0xa << 3)
option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3)
option SMBUS_MEM_DEVICE_INC=1
option SIO_BASE=0x2e
#option SMP=1
option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ
option SMP=1
option IOAPIC=1
option HAVE_MP_TABLE=1
option HAVE_PIRQ_TABLE=1
#option MAX_CPUS=2
option MAX_CPUS=2
option HAVE_MTRR_TABLE=1
#option FINAL_MAINBOARD_FIXUP=1
#option HAVE_HARD_RESET=1
#option STACK_SIZE=0x10000
#option XIP_ROM_SIZE=0x8000
#option XIP_ROM_BASE=0xffff8000
option HAVE_HARD_RESET=1
nooption MEMORY_HOLE
cpu p5

277
src/mainboard/supermicro/p4dc6/cacheramtest.c
View file

@ -8,8 +8,8 @@
#include <arch/io.h>
#include <cpu/p6/msr.h>
#include <cpu/p6/mtrr.h>
#include <arch/cache_ram.h>
#define RAM(type, addr) (*((type *)((unsigned char*)((addr) - CACHE_RAM_BASE))))
#define SMBUS_BUS 0
#define SMBUS_DEVFN ((0x1f << 3) + 3)
@ -48,6 +48,7 @@ static struct smbus_info{
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
void smbus_setup(void)
{
u8 smbus_enable;
@ -81,6 +82,7 @@ static void smbus_wait_until_ready(void)
/* nop */
}
}
static void smbus_wait_until_done(void)
{
unsigned char byte;
@ -412,6 +414,16 @@ struct rdram_reg_values {
u16 channel_b;
};
u16 tparm[5]={0x3a,0x3a,0x3a,0x4a,0x5a};
u16 tcdly1[5]={0,1,2,2,2};
u8 spd_devices[4]={0,0,0,0};
u8 spd_row_col[4]={0,0,0,0};
u8 spd_banks[4]={0,0,0,0};
u8 spd_size[2]={0,0};
int rdram_chips=0;
static void __rdram_run_command(u8 channel, u16 sdevice_id, u16 reg, u16 command)
{
u32 ricm;
@ -583,43 +595,72 @@ static void set_init_bits(int rdram_devices)
static void rdram_read_domain_initialization(int rdram_devices)
{
/* FIXME Figure the rest of this out... */
int i;
for(i = 0; i < rdram_devices; i++) {
struct rdram_reg_values values;
u16 tcdly1_a, tcdly1_b;
unsigned long addr, value;
addr = i*32*1024*1024;
#if 0
RAM(unsigned long, addr) = addr;
value = RAM(unsigned long, addr);
#endif
/* Decrement TCDLY1 for every chip that doesn't have auto-skip=1 */
rdram_read_reg(0, i, REG_SKIP, &values);
tcdly1_a = 2;
tcdly1_b = 2;
if (i >= 7) {
tcdly1_b = 1;
}
if (i >= 10) {
tcdly1_a = 1;
}
if (!(values.channel_a & (1 << 12))) {
tcdly1_a--;
}
if (!(values.channel_b & (1 << 12))) {
tcdly1_b--;
}
rdram_write_reg(0, i, REG_TCDLY1, tcdly1_a, tcdly1_b);
#if 0
value = RAM(unsigned long, addr);
#endif
}
#if 1
/* RDRAM Device Timing */
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RDT, 0x8a);
#endif
u8 rdt=0x8d;
int i,j,k;
u32 data;
u32 *mem;
u8 adj_a[32],adj_b[32];
u8 l=20;
/* Set all the rdram devices to the slowest clock cycles */
rdram_write_reg(0, BCAST, REG_TCDLY1, 0, 0 );
rdram_write_reg(0, BCAST, REG_TPARM, 0x3a, 0x3a);
/* find the slowest RDT timming */
pcibios_write_config_byte(I860_MCH_BUS,I860_MCH_DEVFN,MCH_RDT,rdt);
mem=RAM_ADDR(0x100000);
for(j=0;j<rdram_devices;j++) {
for(k=0,i=4,data=0x00000001;k< ((2048/4)+4);k++,i++,data+=0x00000001) {
if(i>7) {
data-=00000004;
i=0;
}
mem[k]=data;
}
printk_debug("Device = %d, %x, %x\n",j,mem[0],mem[4]);
adj_a[j]=(mem[0]&0x0ff)-1;
adj_b[j]=(mem[4]&0x0ff)-1;
if(adj_a[j]<l) l=adj_a[j];
if(adj_b[j]<l) l=adj_b[j];
if(j<16) {
if(spd_size[0]==32)
mem+=0x1000000; /* add 64 meg */
else
mem+=0x0800000; /* add 32 meg */
}
else {
if(spd_size[1]==32)
mem+=0x1000000; /* add 64 meg */
else
mem+=0x0800000; /* add 32 meg */
}
}
rdt-=l;
printk_debug("RDT = %x, Lowest Offset = %d\n",rdt,l);
for(i=0;i<rdram_devices;i++) {
adj_a[i]-=l;
adj_b[i]-=l;
printk_debug("Device = %d, A Offset = %d, B Offset = %d\n",i,adj_a[i],adj_b[i]);
}
/* RDRAM Device Timing */
pcibios_write_config_byte(I860_MCH_BUS,I860_MCH_DEVFN,MCH_RDT,rdt);
// for(;;) i=1;
for(i = 0; i < rdram_devices; i++) {
rdram_write_reg(0, i, REG_TCDLY1, tcdly1[adj_a[i]], tcdly1[adj_b[i]]);
rdram_write_reg(0, i, REG_TPARM, tparm[adj_a[i]], tparm[adj_b[i]]);
}
for(i = 0; i < rdram_chips; i++) {
for(j = 12; j < 15; j+=2) {
struct rdram_reg_values values;
u16 reg = rdram_regs[j];
rdram_read_reg(0, i, reg, &values);
printk_debug("rdram: %2d reg: %02x %10s a: 0x%04x b: 0x%04x\n",
i, reg, rdram_reg_names[j], values.channel_a, values.channel_b);
}
}
#if 0
rdram_run_command(0, 0, CMD_MCH_RAC_LOAD_RACA_CONFIG);
rdram_run_command(0, 0, CMD_MCH_RAC_LOAD_RACB_CONFIG);
@ -732,18 +773,45 @@ void mch_init(void)
u8 byte;
u16 word;
u32 dword;
/* FIXME unhard code these values */
u16 word2;
int bits1,bits2;
/* Program Group Attribute Registers */
/* 1KB pages, 2x16 banks, 128/144Mbit */
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR0, 0x92);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR1, 0x92);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR2, 0x92);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR3, 0x92);
/* Nothing.. */
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR4, 0x80);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR5, 0x80);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR6, 0x80);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR7, 0x80);
/* Calculate the GAR value */
bits1=(spd_row_col[0]>>4)+(spd_row_col[0]&0x0f)+spd_banks[0];
byte=0x80;
if(bits1==21) {
byte=0xc4;
spd_size[0]=32;
}
else if(bits1==20) {
byte=0x82;
spd_size[0]=16;
}
if(byte!=0x80)
if(spd_banks[0]==5) byte|=0x10;
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR0, byte);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR1, byte);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR2, byte);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR3, byte);
/* Test for 2nd set of rimms */
bits2=(spd_row_col[1]>>4)+(spd_row_col[1]&0x0f)+spd_banks[1];
byte=0x80;
if(bits2==21) {
byte=0xd4;
spd_size[1]=32;
}
else if(bits2==20) {
byte=0x92;
spd_size[1]=16;
}
if(byte!=0x80)
if(spd_banks[2]==5) byte|=0x10;
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR4, byte);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR5, byte);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR6, byte);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR7, byte);
/* The rest are not used because the board has 4 slots & no repeter hubs */
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR8, 0x80);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR9, 0x80);
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR10, 0x80);
@ -777,24 +845,36 @@ void mch_init(void)
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM6, 0x33);
/* RDRAM Device Group Boundary Addresses */
/* 4 groups of 8*16 MB each */
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA0, (0<<11)|(8<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA1, (1<<11)|(16<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA2, (2<<11)|(24<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA3, (3<<11)|(32<<0));
if(bits1==21) word=16;
else word=8;
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA0, (0<<11)|(word));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA1, (1<<11)|(word*2));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA2, (2<<11)|(word*3));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA3, (3<<11)|(word*4));
/* The rest of the groups are empty */
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA4, (4<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA5, (5<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA6, (6<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA7, (7<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA8, (8<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA9, (9<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA10, (10<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA11, (11<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA12, (12<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA13, (13<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA14, (14<<11)|(32<<0));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA15, (15<<11)|(32<<0));
word*=4;
word2=0;
if(bits2==21){
word2=16;
}
else if(bits2==20){
word2=8;
}
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA4, (4<<11)|(word+(word2)));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA5, (5<<11)|(word+(word2*2)));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA6, (6<<11)|(word+(word2*3)));
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA7, (7<<11)|(word+(word2*4)));
/* The rest are filled with the high address */
word=word+(word2*4);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA8, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA9, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA10, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA11, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA12, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA13, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA14, (7<<11)|word);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA15, (7<<11)|word);
/* RDRAM Deice Pool Sizeing Register */
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RDPS, 0x0f);
@ -803,7 +883,8 @@ void mch_init(void)
pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RDT, 0x8e);
/* Top of Memory */
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_TOM, 0x2000);
// pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_TOM, 0x2000);
pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_TOM, word<<8);
/* Error Command Register */
/* Disable reporting errors for now */
@ -825,8 +906,27 @@ void mch_init(void)
static void init_memory(void)
{
int i;
int rdram_devices = 16;
// int rdram_devices = 16;
int rdram_devices=0;
u32 ricm;
for(i=0;i<4;i++)
printk_debug("Devices %d, Row Bits %d, Col Bits %d, Bank Bits %d\n",
spd_devices[i],(spd_row_col[i]>>4),(spd_row_col[i]&0x0f),spd_banks[i]);
for(i=0;i<2;i++) {
if(spd_devices&&(spd_devices[i]==spd_devices[i+2])&&
(spd_row_col[i]==spd_row_col[i+2])&&
(spd_banks[i]==spd_banks[i+2]))
rdram_devices+=spd_devices[i];
}
if(rdram_devices==0){
printk_debug("ERROR - Memory Rimms are not matched.\n");
}
else {
rdram_chips=rdram_devices;
}
printk_debug("RDRAM Chips = %d\n",rdram_chips);
/* 1. Start the clocks */
rdram_run_command(0, 0, CMD_POWERUP_ALL_SEQUENCE);
@ -887,15 +987,15 @@ static void ram_fill(unsigned long start, unsigned long stop)
/*
* Fill.
*/
printk_debug("DRAM fill: %08lx-%08lx\n", start, stop);
printk_spew("DRAM fill: %08lx-%08lx\n", start, stop);
for(addr = start; addr < stop ; addr += 4) {
/* Display address being filled */
if ((addr & 0xffff) == 0)
printk_debug("%08lx\r", addr);
printk_spew("%08lx\r", addr);
RAM(unsigned long, addr) = addr;
};
/* Display final address */
printk_debug("%08lx\nDRAM filled\n", addr);
printk_spew("%08lx\nDRAM filled\n", addr);
}
@ -907,22 +1007,22 @@ static int ram_verify(unsigned long start, unsigned long stop, int max_errors)
/*
* Verify.
*/
printk_debug("DRAM verify: %08lx-%08lx\n", start, stop);
printk_spew("DRAM verify: %08lx-%08lx\n", start, stop);
for(addr = start; addr < stop ; addr += 4) {
unsigned long value;
/* Display address being tested */
if ((addr & 0xffff) == 0)
printk_debug("%08lx\r", addr);
printk_spew("%08lx\r", addr);
value = RAM(unsigned long, addr);
if (value != addr) {
if (++errors <= max_errors) {
/* Display address with error */
printk_debug("%08lx:%08lx\n", addr, value);
printk_err("%08lx:%08lx\n", addr, value);
}
}
}
/* Display final address */
printk_debug("%08lx\nDRAM verified %d/%d errors\n",
printk_spew("%08lx\nDRAM verified %d/%d errors\n",
addr, errors, (stop - start)/4);
return errors;
}
@ -935,22 +1035,22 @@ static int ram_odd_verify(unsigned long start, unsigned long stop, int max_error
/*
* Verify.
*/
printk_debug("DRAM odd verify: %08lx-%08lx\n", start, stop);
printk_spew("DRAM odd verify: %08lx-%08lx\n", start, stop);
for(addr = start; addr < stop ; addr += 4) {
unsigned long value;
/* Display address being tested */
if ((addr & 0xffff) == 0)
printk_debug("%08lx\r", addr);
printk_spew("%08lx\r", addr);
value = RAM(unsigned long, addr);
if (value != (addr ^ 0x20)) {
if (++errors < max_errors) {
/* Display address with error */
printk_debug("%08lx:%08lx\n", addr, value);
printk_err("%08lx:%08lx\n", addr, value);
}
}
}
/* Display final address */
printk_debug("%08lx\nDRAM odd verified %d/%d errors\n",
printk_spew("%08lx\nDRAM odd verified %d/%d errors\n",
addr, errors, (stop - start)/4);
return 0;
}
@ -964,12 +1064,12 @@ static int ramcheck(unsigned long start, unsigned long stop, int max_errors)
* test than a "Is my DRAM faulty?" test. Not all bits
* are tested. -Tyson
*/
printk_debug("Testing DRAM : %08lx-%08lx\n",
printk_spew("Testing DRAM : %08lx-%08lx\n",
start, stop);
ram_fill(start, stop);
result = ram_verify(start, stop, max_errors);
printk_debug("Done.\n");
printk_spew("Done.\n");
return result;
}
@ -982,13 +1082,13 @@ static int ramcheck2(unsigned long start, unsigned long stop, int max_errors)
* test than a "Is my DRAM faulty?" test. Not all bits
* are tested. -Tyson
*/
printk_debug("Testing DRAM : %08lx-%08lx\n",
printk_spew("Testing DRAM : %08lx-%08lx\n",
start, stop);
ram_fill(start, stop);
result = ram_odd_verify(start, stop, max_errors);
printk_debug("Done.\n");
printk_spew("Done.\n");
return result;
}
@ -1043,15 +1143,15 @@ void cache_ram_start(void)
printk_info("Selecting rdram i2c bus\n");
select_rdram_i2c();
#if 0
for(j = SMBUS_MEM_DEVICE_0; j < SMBUS_MEM_DEVICE_0 + 8; j++) {
#if 1
for(j = SMBUS_MEM_DEVICE_0; j < SMBUS_MEM_DEVICE_0 + 4; j++) {
int status = 0;
if ((j == 0x1b) || 0) {
printk_debug("skipping device: %02x\n", j);
continue;
}
printk_debug("smbus_device: %02x\n", j);
for(i = 0; (i < 256) && (status == 0); i++) {
for(i = 0; (i < 128) && (status == 0); i++) {
unsigned char byte;
status = smbus_read_byte(j, i, &byte);
if (status != 0) {
@ -1062,6 +1162,9 @@ void cache_ram_start(void)
if ((i &0x0f) == 0x0f) {
printk_debug("\n");
}
if(i==99) spd_devices[j-SMBUS_MEM_DEVICE_0]=byte;
if(i==4) spd_row_col[j-SMBUS_MEM_DEVICE_0]=byte;
if(i==5) spd_banks[j-SMBUS_MEM_DEVICE_0]=byte&0x0f;
}
}
printk_debug("\n");
@ -1127,8 +1230,8 @@ void cache_ram_start(void)
#if 0
error |= ramcheck(0x00000000, 0x00080000, 20);
#endif
#if 1
for(i = 0; i < 16; i++) {
#if 0
for(i = 0; i < rdram_chips; i++) {
for(j = 0; j < sizeof(rdram_regs)/sizeof(rdram_regs[0]); j++) {
struct rdram_reg_values values;
u16 reg = rdram_regs[j];

23
src/mainboard/supermicro/p4dc6/mainboard.c
View file

@ -1,10 +1,33 @@
#include <arch/io.h>
#include <part/mainboard.h>
#include <printk.h>
#include <pci.h>
#include <pci_ids.h>
#include <southbridge/intel/82801.h>
#include <arch/smp/mpspec.h>
unsigned long initial_apicid[MAX_CPUS] =
{
0, 6
};
void mainboard_fixup(void)
{
ich2_enable_ioapic();
ich2_enable_serial_irqs();
ich2_enable_ide(1,1);
rtc_init();
ich2_lpc_route_dma(0xff);
isa_dma_init();
printk_notice("Please add a mainboard_fixup!\n");
return;
}
void hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
return;
}

49
src/mainboard/supermicro/p4dc6/mtrr_values.c Normal file
View file

@ -0,0 +1,49 @@
#include <cpu/p6/mtrr.h>
/* We want to cache memory as efficiently as possible.
*/
#define RAM MTRR_TYPE_WRBACK
/* We can't use Write Combining on a legacy frame buffer because
* it is incompatible with EGA 16 color video modes...
*/
#define FB MTRR_TYPE_UNCACHABLE
/* For areas that are supposed to cover roms it makes no
* sense to cache writes.
*/
#define ROM MTRR_TYPE_WRPROT
unsigned char fixed_mtrr_values[][4] = {
/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */
{FB, FB, FB, FB}, {FB, FB, FB, FB},
/* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
};

1
src/mainboard/technoland/sbc710/Config
View file

@ -8,6 +8,7 @@ option SERIAL_SUPERIO_BASEADDRESS=0x370
mainboardinit superio/winbond/w83977ef/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc

1
src/mainboard/tyan/guiness/Config
View file

@ -11,6 +11,7 @@ mainboardinit northbridge/amd/amd76x/mpinit.inc
mainboardinit southbridge/amd/amd766/lpc_com1.inc
mainboardinit superio/winbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
#mainboardinit ram/ramtest.inc
#mainboardinit mainboard/tyan/guiness/do_ramtest.inc
mainboardinit southbridge/amd/amd766/smbus.inc

6
src/mainboard/tyan/guiness/mainboard.c
View file

@ -5,6 +5,12 @@
#include <delay.h>
#include <part/mainboard.h>
#include <part/hard_reset.h>
#include <arch/smp/mpspec.h>
unsigned long initial_apicid[MAX_CPUS] =
{
0, 1
};
static void lpc_routing_fixup(void)
{

1
src/mainboard/tyan/s1834/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/winbond/w83977ef/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit northbridge/via/vt8601/raminit.inc
#mainboardinit ram/ramtest.inc
#mainboardinit cpu/p6/earlymtrr.inc

8
src/mainboard/tyan/s1834/crt0.S
View file

@ -29,7 +29,7 @@
#include <pc80/serial.inc>
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -52,7 +52,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -64,7 +64,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -88,7 +88,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

1
src/mainboard/tyan/s1846/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/NSC/pc87309/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc

9
src/mainboard/tyan/s1846/crt0.S
View file

@ -29,8 +29,9 @@
#include <superio/NSC/pc87309/setup_serial.inc>
#include <pc80/serial.inc>
#include <arch/i386/lib/console.inc>
TTYS0_TX_STRING($ttyS0_test)
CONSOLE_DEBUG_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
@ -66,7 +67,7 @@
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
CONSOLE_DEBUG_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
@ -78,7 +79,7 @@
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
CONSOLE_DEBUG_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
@ -102,7 +103,7 @@
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
CONSOLE_DEBUG_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp

1
src/mainboard/via/vt5292/Config
View file

@ -6,6 +6,7 @@ ldscript cpu/i386/reset16.lds
mainboardinit superio/via/vt82c686/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge via/vt8601
southbridge via/vt82c686
superio via/vt82c686

1
src/mainboard/via/vt5426/Config
View file

@ -4,6 +4,7 @@ ldscript cpu/i386/entry16.lds
mainboardinit superio/via/vt82c686/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
northbridge via/vt8601
southbridge via/vt82c686
superio via/vt82c686

40
src/northbridge/amd/amd76x/raminit.inc
View file

@ -17,15 +17,15 @@ dump_sdram_config:
dump_sdram_config_byte_header:
testb $0x0f,%bl
jnz dump_sdram_config_byte
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
movl %ebx, %eax
CALLSP(ttys0_tx_hex32)
TTYS0_TX_CHAR($':')
TTYS0_TX_CHAR($' ')
CONSOLE_DEBUG_TX_CHAR($':')
CONSOLE_DEBUG_TX_CHAR($' ')
dump_sdram_config_byte:
TTYS0_TX_CHAR($' ')
CONSOLE_DEBUG_TX_CHAR($' ')
movl %ebx, %eax
PCI_READ_CONFIG_BYTE
CALLSP(ttys0_tx_hex8)
@ -33,8 +33,8 @@ dump_sdram_next_byte:
incl %ebx
cmpl $0x00000200, %ebx
jne dump_sdram_config_byte_header
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
RET_LABEL(dump_sdram_config)
#endif
@ -483,15 +483,15 @@ ram_set_registers:
ram_set_one_register:
#if DEBUG_RAM_CONFIG
movl %ebx, %esi
TTYS0_TX_CHAR($'C')
TTYS0_TX_CHAR($':')
CONSOLE_DEBUG_TX_CHAR($'C')
CONSOLE_DEBUG_TX_CHAR($':')
movl 0(%esi), %eax
CALLSP(ttys0_tx_hex32)
TTYS0_TX_CHAR($':')
CONSOLE_DEBUG_TX_CHAR($':')
movl 4(%esi), %eax
CALLSP(ttys0_tx_hex32)
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
movl %esi, %ebx
#endif /* DEBUG_RAM_CONFIG */
movl 0(%ebx), %eax
@ -507,16 +507,16 @@ ram_set_one_register_start:
ram_set_one_mainboard_register:
#if DEBUG_RAM_CONFIG
movl %ebx, %esi
TTYS0_TX_CHAR($'M')
TTYS0_TX_CHAR($'C')
TTYS0_TX_CHAR($':')
CONSOLE_DEBUG_TX_CHAR($'M')
CONSOLE_DEBUG_TX_CHAR($'C')
CONSOLE_DEBUG_TX_CHAR($':')
movl 0(%esi), %eax
CALLSP(ttys0_tx_hex32)
TTYS0_TX_CHAR($':')
CONSOLE_DEBUG_TX_CHAR($':')
movl 4(%esi), %eax
CALLSP(ttys0_tx_hex32)
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
movl %esi, %ebx
#endif /* DEBUG_RAM_CONFIG */
movl 0(%ebx), %eax
@ -1441,7 +1441,7 @@ get_dimm_row_cycle_setting_low:
dimm_row_new_cycle_setting_msg:
.string "\r\n Newly defined SPD byte 41 populated please update the code to handle this\r\n"
get_dimm_row_cycle_setting_new:
TTYS0_TX_STRING($dimm_row_new_cycle_setting_msg)
CONSOLE_DEBUG_TX_STRING($dimm_row_new_cycle_setting_msg)
/* fall through */
get_dimm_row_cycle_setting_error:
@ -2057,7 +2057,7 @@ enable_sdram_wait:
testl $(1 << 23), %eax /* Wait until the mode register is set */
jnz enable_sdram_wait
TTYS0_TX_STRING($ram_enabled)
CONSOLE_DEBUG_TX_STRING($ram_enabled)
RET_LABEL(enable_sdram)

46
src/northbridge/intel/82815ep/raminit.inc
View file

@ -28,24 +28,24 @@ jmp intel_815_out
// trashed : ax, bx, dx, sp
#define NEWLINE \
TTYS0_TX_CHAR($'\r') ;\
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r') ;\
CONSOLE_DEBUG_TX_CHAR($'\n')
#define PRINT_REG(reg) \
TTYS0_TX_HEX8($reg) ; \
TTYS0_TX_CHAR($':') ; \
CONSOLE_DEBUG_TX_HEX8($reg) ; \
CONSOLE_DEBUG_TX_CHAR($':') ; \
mov $reg, %eax ; \
PCI_READ_CONFIG_BYTE ; \
TTYS0_TX_HEX8(%al) ; \
CONSOLE_DEBUG_TX_HEX8(%al) ; \
NEWLINE
#define PRINT_REG_WORD(reg) \
TTYS0_TX_HEX8($reg) ; \
TTYS0_TX_CHAR($':') ; \
CONSOLE_DEBUG_TX_HEX8($reg) ; \
CONSOLE_DEBUG_TX_CHAR($':') ; \
mov $reg, %eax ; \
PCI_READ_CONFIG_WORD ; \
andl $0xffff, %eax ; \
TTYS0_TX_HEX32(%eax) ; \
CONSOLE_DEBUG_TX_HEX32(%eax) ; \
NEWLINE
#define FIRST_NORMAL_REFERENCE()
@ -238,19 +238,19 @@ ram_pass: .string "--- SDRAM TEST PASSED \r\n"
enable_sdram:
// Enterring NOP command enable mode
TTYS0_TX_STRING($ram_enable_1)
CONSOLE_DEBUG_TX_STRING($ram_enable_1)
SET_RAM_COMMAND(RAM_COMMAND_NOP)
RAMREAD
MYDELAY($400) // wait a while (minimal 200us)
// Precharge all
TTYS0_TX_STRING($ram_enable_2)
CONSOLE_DEBUG_TX_STRING($ram_enable_2)
SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE)
RAMREAD
// 8 auto refresh command "CAS before RAS"
TTYS0_TX_STRING($ram_enable_3)
CONSOLE_DEBUG_TX_STRING($ram_enable_3)
SET_RAM_COMMAND(RAM_COMMAND_CBR)
RAMREAD
@ -271,7 +271,7 @@ enable_sdram:
MYDELAY($100)
// Mode register set
TTYS0_TX_STRING($ram_enable_4)
CONSOLE_DEBUG_TX_STRING($ram_enable_4)
SET_RAM_COMMAND(RAM_COMMAND_MRS)
/* MAx[14:0] lines,
@ -293,10 +293,10 @@ enable_sdram:
shll $3, %eax
movl (%eax), %ebx // MRS comand to sdram
// TTYS0_TX_HEX32(%eax)
// CONSOLE_DEBUG_TX_HEX32(%eax)
// Normal operation mode
TTYS0_TX_STRING($ram_enable_5)
CONSOLE_DEBUG_TX_STRING($ram_enable_5)
SET_RAM_COMMAND(RAM_COMMAND_NORMAL_0) // SPD: 12 (refresh rate)
DO_READ($0x0)
@ -304,13 +304,13 @@ enable_sdram:
DO_WRITE($0x0, $0x0)
DO_READ($0x0)
TTYS0_TX_HEX32(%eax)
CONSOLE_DEBUG_TX_HEX32(%eax)
NEWLINE
DO_WRITE($0xff, $0xff)
DO_READ($0xff)
TTYS0_TX_HEX32(%eax)
CONSOLE_DEBUG_TX_HEX32(%eax)
NEWLINE
*/
@ -328,23 +328,23 @@ enable_sdram:
// verify..
movl (%esi), %edi
TTYS0_TX_HEX32(%edi)
CONSOLE_DEBUG_TX_HEX32(%edi)
movl 8(%esi), %edi
TTYS0_TX_HEX32(%edi)
CONSOLE_DEBUG_TX_HEX32(%edi)
movl 16(%esi), %edi
TTYS0_TX_HEX32(%edi)
CONSOLE_DEBUG_TX_HEX32(%edi)
cmpl $0x12345678, %edi
je pass
fail:
TTYS0_TX_HEX32(%edi)
TTYS0_TX_STRING($ram_fail)
CONSOLE_DEBUG_TX_HEX32(%edi)
CONSOLE_DEBUG_TX_STRING($ram_fail)
jmp doneDetection
pass:
TTYS0_TX_HEX32(%edi)
TTYS0_TX_STRING($ram_pass)
CONSOLE_DEBUG_TX_HEX32(%edi)
CONSOLE_DEBUG_TX_STRING($ram_pass)
doneDetection:
#endif // 0

3
src/northbridge/intel/82860/Config
View file

@ -1 +1,4 @@
mainboardinit arch/i386/lib/set_memory_size_noop.inc
mainboardinit arch/i386/lib/cpu_reset.inc
object northbridge.o

1
src/northbridge/intel/82860/northbridge.c
View file

@ -8,7 +8,6 @@ unsigned long sizeram(void)
unsigned long size;
unsigned short word;
printk_notice("\nsizeram!!!\n");
/* Read TOM */
/* How should we handle > 4GB of ram? */
pcibios_read_config_word(0, 0, 0xc4, &word);

10
src/northbridge/intel/82860/reset_test.inc Normal file
View file

@ -0,0 +1,10 @@
#define MCH_RICM 0x94
#define RICM_DONE (1 << 27)
/* If I have already booted once skip a bunch of initialization */
/* To see if I have already booted I check to see if memory
* has been enabled.
*/
movl $MCH_RICM, %eax
PCI_READ_CONFIG_DWORD
testl $RICM_DONE, %eax
jnz __cpu_reset

263
src/pc80/serial.inc
View file

@ -55,268 +55,6 @@
outb %al, %dx
/* uses: esp, ax, dx */
#define TTYS0_TX_CHAR(byte) \
mov byte, %al ; \
CALLSP(ttys0_tx_al)
/* uses: ax, dx */
#define TTYS0_INLINE_TX_CHAR(byte) \
mov byte, %al ; \
TTYS0_TX_AL
/* uses: esp, ax, dx */
#define TTYS0_TX_HEX8(byte) \
mov byte, %al ; \
CALLSP(ttys0_tx_hex8)
/* uses: ax, dx */
#define TTYS0_INLINE_TX_HEX8(byte) \
mov byte, %al ; \
mov $TTYS0_SCR, %dx ; \
outb %al, %dx ; \
shr $4, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
mov $TTYS0_SCR, %dx ; \
inb %dx, %al ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
mov $TTYS0_SCR, %dx ; \
inb %dx, %al
/* uses: esp, eax, ebx, dx */
#define TTYS0_TX_HEX32(lword) \
mov lword, %eax ; \
CALLSP(ttys0_tx_hex32)
/* uses: eax, lword, dx */
#define TTYS0_INLINE_TX_HEX32(lword) \
mov lword, %eax ; \
shr $28, %eax ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
shr $24, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
shr $20, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
shr $16, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
shr $12, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
shr $8, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
shr $4, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL ; \
; \
mov lword, %eax ; \
and $0x0f, %al ; \
add $'0', %al ; \
cmp $'9', %al ; \
jle 9f ; \
add $39, %al ; \
9: ; \
TTYS0_TX_AL
/* uses: esp, ebx, ax, dx */
#define TTYS0_TX_STRING(string) \
mov string, %ebx ; \
CALLSP(ttys0_tx_string)
/* uses: ebx, ax, dx */
#define TTYS0_INLINE_TX_STRING(string) \
movl string, %ebx ; \
10: movb (%ebx), %al ; \
incl %ebx ; \
testb %al, %al ; \
jz 11f ; \
TTYS0_TX_AL ; \
jmp 10b ; \
11:
/* uses: esp, ax, dx */
ttys0_tx_al:
TTYS0_TX_AL
RETSP
/* uses: esp, ax, dx */
ttys0_tx_hex8:
mov $TTYS0_SCR, %dx
outb %al, %dx
shr $4, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov $TTYS0_SCR, %dx
inb %dx, %al
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
RETSP
/* uses: esp, ebx, eax, dx */
ttys0_tx_hex32:
mov %eax, %ebx
shr $28, %eax
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
shr $24, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
shr $20, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
shr $16, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
shr $12, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
shr $8, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
shr $4, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
mov %ebx, %eax
and $0x0f, %al
add $'0', %al
cmp $'9', %al
jle 9f
add $39, %al
9:
TTYS0_TX_AL
RETSP
/* Uses esp, ebx, ax, dx */
ttys0_tx_string:
mov (%ebx), %al
inc %ebx
cmp $0, %al
jne 9f
RETSP
9:
TTYS0_TX_AL
jmp ttys0_tx_string
serial0:
/* Set 115.2Kbps,8n1 */
/* Set 8bit, 1 stop bit, no parity, DLAB */
@ -337,5 +75,4 @@ serial0:
mov $(TTYS0_LCS & 0x7f), %al
out %al, %dx
TTYS0_TX_STRING($ttyS0_test)

72
src/ram/ramtest.inc
View file

@ -20,61 +20,52 @@ ramtest:
mov %ebx, %edi
mov %esp, %ebp
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($rt_test)
TTYS0_TX_HEX32(%esi)
TTYS0_TX_CHAR($'-')
TTYS0_TX_HEX32(%edi)
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_INFO_TX_STRING($rt_test)
CONSOLE_INFO_TX_HEX32(%esi)
CONSOLE_INFO_TX_CHAR($'-')
CONSOLE_INFO_TX_HEX32(%edi)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
/* ============== Fill ram block ==== */
TTYS0_TX_STRING($rt_fill)
#endif
CONSOLE_INFO_TX_STRING($rt_fill)
mov %esi, %ebx
1:
cmp $0, %bx
jne 2f
#ifdef SERIAL_CONSOLE
/* Display address being filled */
/* TTYS0_TX_HEX32(arg) will overwrite %ebx with arg */
/* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */
TTYS0_TX_HEX32(%ebx)
TTYS0_TX_CHAR($'\r')
#endif
CONSOLE_INFO_TX_HEX32(%ebx)
CONSOLE_INFO_TX_CHAR($'\r')
2:
mov %ebx, (%ebx)
add $4, %ebx
cmp %edi, %ebx
jl 1b
#ifdef SERIAL_CONSOLE
/* Display final address */
TTYS0_TX_HEX32(%edi)
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_INFO_TX_HEX32(%edi)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
/* ========= Verify ram block ========== */
TTYS0_TX_STRING($rt_verify)
#endif
CONSOLE_INFO_TX_STRING($rt_verify)
mov %esi, %ebx
1:
cmp $0, %bx
jne 2f
#ifdef SERIAL_CONSOLE
/* Display address being tested */
TTYS0_TX_HEX32(%ebx)
TTYS0_TX_CHAR($'\r')
#endif
CONSOLE_INFO_TX_HEX32(%ebx)
CONSOLE_INFO_TX_CHAR($'\r')
2:
cmp %ebx, (%ebx)
jne 4f
@ -83,48 +74,39 @@ ramtest:
cmp %edi, %ebx
jl 1b
#ifdef SERIAL_CONSOLE
/* Display final address */
TTYS0_TX_HEX32(%edi)
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
#endif
CONSOLE_INFO_TX_HEX32(%edi)
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
jmp 6f
4:
#ifdef SERIAL_CONSOLE
/* Display address with error */
TTYS0_TX_HEX32(%ebx)
TTYS0_TX_CHAR($':')
CONSOLE_INFO_TX_HEX32(%ebx)
CONSOLE_INFO_TX_CHAR($':')
/* Display data in address with error */
/* TTYS0_TX_HEX32(arg) will overwrite %ebx with arg */
/* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */
mov %ebx, %esi
mov 0(%ebx), %eax
TTYS0_TX_HEX32(%eax)
CONSOLE_INFO_TX_HEX32(%eax)
mov %esi, %ebx
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
#endif
CONSOLE_INFO_TX_CHAR($'\r')
CONSOLE_INFO_TX_CHAR($'\n')
sub $1, %ecx
jz 5f
jmp 3b
5:
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($rt_toomany)
#endif
CONSOLE_INFO_TX_STRING($rt_toomany)
intel_chip_post_macro(0xf1)
jmp .Lhlt
6:
#ifdef SERIAL_CONSOLE
TTYS0_TX_STRING($rt_done)
#endif
CONSOLE_INFO_TX_STRING($rt_done)
mov %ebp, %esp
#endif
RETSP

28
src/sdram/generic_dump_spd.inc
View file

@ -1,36 +1,36 @@
dump_spd_registers:
movl $((0 << 8) | SMBUS_MEM_DEVICE_START), %ebx
dump_spd_reg_dimm:
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
TTYS0_TX_CHAR($'d')
TTYS0_TX_CHAR($'i')
TTYS0_TX_CHAR($'m')
TTYS0_TX_CHAR($'m')
TTYS0_TX_CHAR($' ')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'d')
CONSOLE_DEBUG_TX_CHAR($'i')
CONSOLE_DEBUG_TX_CHAR($'m')
CONSOLE_DEBUG_TX_CHAR($'m')
CONSOLE_DEBUG_TX_CHAR($' ')
movb %bl, %al
CALLSP(ttys0_tx_hex8)
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
dump_spd_reg_byte:
CALLSP(smbus_read_byte)
jz dump_spd_reg_next_dimm
CALLSP(ttys0_tx_hex8)
TTYS0_TX_CHAR($' ')
CONSOLE_DEBUG_TX_CHAR($' ')
incb %bh
testb $0x0F, %bh
jnz dump_spd_reg_next_byte
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
dump_spd_reg_next_byte:
cmpb $0, %bh
jne dump_spd_reg_byte
dump_spd_reg_next_dimm:
TTYS0_TX_CHAR($'\r')
TTYS0_TX_CHAR($'\n')
CONSOLE_DEBUG_TX_CHAR($'\r')
CONSOLE_DEBUG_TX_CHAR($'\n')
xorb %bh, %bh
add $SMBUS_MEM_DEVICE_INC, %bl
cmpb $(SMBUS_MEM_DEVICE_END + SMBUS_MEM_DEVICE_INC), %bl

14
src/sdram/generic_sdram.inc
View file

@ -10,25 +10,25 @@ ram_6: .string "Ram6\r\n"
no_memory_str: .string "No memory!\r\n"
no_memory: TTYS0_TX_STRING($no_memory_str)
no_memory: CONSOLE_DEBUG_TX_STRING($no_memory_str)
1: hlt /* stick here.. */
jmp 1b
ram_initialize:
/* this sets up the dram. */
TTYS0_TX_STRING($ram_1)
CONSOLE_DEBUG_TX_STRING($ram_1)
/* Now, set registers we can set once to reasonable values */
CALL_LABEL(ram_set_registers)
TTYS0_TX_STRING($ram_2)
CONSOLE_DEBUG_TX_STRING($ram_2)
/* Now set those things we can auto detect */
CALL_LABEL(ram_set_spd_registers)
TTYS0_TX_STRING($ram_3)
CONSOLE_DEBUG_TX_STRING($ram_3)
/* Now that everything is setup enable the SDRAM
* Some chipsets do the work for us while on others
@ -36,15 +36,15 @@ ram_initialize:
*/
CALL_LABEL(enable_sdram)
TTYS0_TX_STRING($ram_4)
CONSOLE_DEBUG_TX_STRING($ram_4)
FIRST_NORMAL_REFERENCE()
TTYS0_TX_STRING($ram_5)
CONSOLE_DEBUG_TX_STRING($ram_5)
/* Finally enable refresh */
ENABLE_REFRESH()
SPECIAL_FINISHUP()
TTYS0_TX_STRING($ram_6)
CONSOLE_DEBUG_TX_STRING($ram_6)

10
src/sdram/generic_sdram_enable.inc
View file

@ -21,7 +21,7 @@ enable_sdram:
turn on the dram and wait a while (this from the intel book)
turn power on and set the nop bit too
*/
TTYS0_TX_STRING($ram_enable_1)
CONSOLE_DEBUG_TX_STRING($ram_enable_1)
/* SDRAMC */
SET_RAM_COMMAND(RAM_COMMAND_NOP)
@ -35,7 +35,7 @@ enable_sdram:
/* wait until the all banks idle state... */
TTYS0_TX_STRING($ram_enable_2)
CONSOLE_DEBUG_TX_STRING($ram_enable_2)
/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
@ -49,7 +49,7 @@ enable_sdram:
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
TTYS0_TX_STRING($ram_enable_3)
CONSOLE_DEBUG_TX_STRING($ram_enable_3)
/* mode register set */
SET_RAM_MODE_REGISTER
@ -62,12 +62,12 @@ enable_sdram:
* MAx[12:7] == 0
*/
TTYS0_TX_STRING($ram_enable_4)
CONSOLE_DEBUG_TX_STRING($ram_enable_4)
/* normal operation */
SET_RAM_COMMAND(RAM_COMMAND_NONE)
TTYS0_TX_STRING($ram_enable_5)
CONSOLE_DEBUG_TX_STRING($ram_enable_5)
RET_LABEL(enable_sdram)
generic_sdram_enable_out:

8
src/sdram/generic_zero_ecc_sdram.inc
View file

@ -6,7 +6,7 @@ ecc_ram_3: .string "ecc_ram_3\r\n"
ecc_ram_4: .string "ecc_ram_4\r\n"
ecc_ram_initialize:
TTYS0_TX_STRING($ecc_ram_1)
CONSOLE_DEBUG_TX_STRING($ecc_ram_1)
CALL_LABEL(get_ecc_ram_size_bytes_ebx)
/* If we don't have an ECC SDRAM size skip the zeroing */
@ -53,7 +53,7 @@ ecc_ram_initialize:
movl %eax, %cr0
/* Now zero the memory */
TTYS0_TX_STRING($ecc_ram_2)
CONSOLE_DEBUG_TX_STRING($ecc_ram_2)
cld
#if !defined(HAVE_PC80_MEMORY_HOLE)
@ -79,7 +79,7 @@ ecc_ram_initialize:
rep stosl
#endif /* HAVE_PC80_MEMORY_HOLE */
TTYS0_TX_STRING($ecc_ram_3)
CONSOLE_DEBUG_TX_STRING($ecc_ram_3)
/* Change caching on memory from write-combining to write-back. */
/* Disable the cache while we set up a new MTRR over memory */
@ -98,5 +98,5 @@ ecc_ram_initialize:
movl %eax, %cr0
zero_ecc_ram_out:
TTYS0_TX_STRING($ecc_ram_4)
CONSOLE_DEBUG_TX_STRING($ecc_ram_4)

1
src/southbridge/intel/82801/82801.h
View file

@ -1,2 +1,3 @@
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
#define GEN_CNTL 0xd0

1
src/southbridge/intel/82801/Config
View file

@ -1,3 +1,4 @@
object nvram.o
object ich2_ioapic.o
object ich2_lpc.o
object ich2_ide.o

24
src/southbridge/intel/82801/ich2_ide.c Normal file
View file

@ -0,0 +1,24 @@
#include <pci.h>
#include <pci_ids.h>
#include <southbridge/intel/82801.h>
void ich2_enable_ide(int enable_a, int enable_b)
{
struct pci_dev *dev;
dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F1, 0);
if (dev != NULL) {
/* Enable ide devices so the linux ide driver will work */
u16 word;
/* enable ide0 */
pci_read_config_word(dev, 0x40, &word);
word &= ~(1 << 15);
word |= ((!!enable_a) << 15);
pci_write_config_word(dev, 0x40, word);
/* enable ide1 */
pci_read_config_word(dev, 0x42, &word);
word &= ~(1 << 15);
word |= ((!!enable_b) << 15);
pci_write_config_word(dev, 0x42, word);
}
}

2
src/southbridge/intel/82801/ich2_ioapic.c
View file

@ -1,6 +1,8 @@
#include <pci.h>
#include <pci_ids.h>
#include <southbridge/intel/82801.h>
#include "82801.h"
void ich2_enable_ioapic(void)
{
struct pci_dev *dev;

22
src/southbridge/intel/82801/ich2_lpc.c
View file

@ -1,13 +1,33 @@
#include <pci.h>
#include <pci_ids.h>
#include <southbridge/intel/82801.h>
#include "82801.h"
void ich2_enable_serial_irqs(void)
{
struct pci_dev *dev;
u32 dword;
dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F0, 0);
if (!dev) {
return;
}
pci_write_config_byte(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
}
void ich2_lpc_route_dma(unsigned char mask)
{
struct pci_dev *dev;
u16 word;
int i;
dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F0, 0);
if (!dev) {
return;
}
pci_read_config_word(dev, PCI_DMA_CFG, &word);
word &= ((1 << 10) - (1 << 8));
for(i = 0; i < 8; i++) {
if (i == 4)
continue;
word |= ((mask & (1 << i))? 3:1) << (i*2);
}
pci_write_config_word(dev, PCI_DMA_CFG, word);
}

188
src/southbridge/via/vt82c686/southbridge.c
View file

@ -1,29 +1,54 @@
#include <pci.h>
#include <pc80/keyboard.h>
#include <printk.h>
#include <pci_ids.h>
void keyboard_on()
{
volatile unsigned char regval;
struct pci_dev *dev;
printk_debug("keyboard_on\n");
/* regval = intel_conf_readb(0x8000385A); */
/*regval |= 0x01; */
regval = 0xff;
intel_conf_writeb(0x8000385A, regval);
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev) {
pci_write_config_byte(dev, 0x5a, regval);
}
/* disable USB1 */
intel_conf_writeb(0x80003A3C, 0x00);
intel_conf_writeb(0x80003A04, 0x00);
regval = intel_conf_readb(0x80003848);
regval |= 0x04;
intel_conf_writeb(0x80003848, regval);
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
if (dev) {
pci_write_config_byte(dev, 0x3c, 0x00);
}
if (dev) {
pci_write_config_byte(dev, 0x04, 0x00);
}
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev) {
pci_read_config_byte(dev, 0x048, &regval);
regval |= 0x04;
pci_write_config_byte(dev, 0x048, regval);
}
/* disable USB2 */
intel_conf_writeb(0x80003B3C, 0x00);
intel_conf_writeb(0x80003B04, 0x00);
regval = intel_conf_readb(0x80003885);
regval |= 0x10;
intel_conf_writeb(0x80003885, regval);
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev);
if (dev) {
pci_write_config_byte(dev, 0x3c, 0x00);
}
if (dev) {
pci_write_config_byte(dev, 0x04, 0x00);
}
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev) {
pci_read_config_byte(dev, 0x85, &regval);
regval |= 0x10;
pci_write_config_byte(dev, 0x85, regval);
}
pc_keyboard_init();
@ -34,91 +59,128 @@ void nvram_on()
/* the VIA 686A South has a very different nvram setup than the piix4e ... */
/* turn on ProMedia nvram. */
/* TO DO: use the PciWriteByte function here. */
intel_conf_writeb(0x80003843, 0xFF);
struct pci_dev *dev;
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev) {
pci_write_config_byte(dev, 0x43, 0xc0);
}
}
void southbridge_fixup()
{
unsigned int devfn;
unsigned char enables;
struct pci_dev *dev;
struct pci_dev *dev0;
struct pci_dev dev_cpy;
// enable the internal I/O decode
// to do: use the pcibios_find function here, instead of
// hard coding the devfn.
devfn = PCI_DEVFN(7, 0);
enables = pcibios_read_config_byte(0, devfn, 0x81, &enables);
enables |= 0x80;
pcibios_write_config_byte(0, devfn, 0x81, enables);
dev0=0;
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, 0);
if (dev) {
dev0=dev;
memcpy(&dev_cpy,dev,sizeof(dev_cpy));
pci_read_config_byte(dev, 0x81, &enables);
enables |= 0x80;
pci_write_config_byte(dev, 0x81, enables);
}
else
printk_debug("IDE pci_find_device function 0 failed\n");
#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS
// enable com1 and com2.
enables = pcibios_read_config_byte(0, devfn, 0x83, &enables);
// 0x80 is enable com port b, 0x1 is to make it com2, 0x8 is enable com port a as com1
enables = 0x80 | 0x1 | 0x8 ;
pcibios_write_config_byte(0, devfn, 0x83, enables);
if (dev) {
pci_write_config_byte(0, devfn, 0x83, enables);
}
// note: this is also a redo of some port of assembly, but we want everything up.
// set com1 to 115 kbaud
// not clear how to do this yet.
// forget it; done in assembly.
#endif
// enable IDE, since Linux won't do it.
// First do some more things to devfn (7,0)
// note: this should already be cleared, according to the book.
pcibios_read_config_byte(0, devfn, 0x48, &enables);
printk_debug("IDE enable in reg. 48 is 0x%x\n", enables);
enables &= ~2; // need manifest constant here!
printk_debug("set IDE reg. 48 to 0x%x\n", enables);
pcibios_write_config_byte(0, devfn, 0x48, enables);
if (dev) {
pci_read_config_byte(dev, 0x48, &enables);
printk_debug("IDE enable in reg. 48 is 0x%x\n", enables);
enables &= ~2; // need manifest constant here!
printk_debug("set IDE reg. 48 to 0x%x\n", enables);
pci_write_config_byte(dev, 0x48, enables);
}
// set default interrupt values (IDE)
pcibios_read_config_byte(0, devfn, 0x4a, &enables);
printk_debug("IRQs in reg. 4a are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xf;
enables |= 4;
printk_debug("setting reg. 4a to 0x%x\n", enables);
pcibios_write_config_byte(0, devfn, 0x4a, enables);
if (dev) {
pci_read_config_byte(dev, 0x4a, &enables);
printk_debug("IRQs in reg. 4a are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xff;
enables |= 0x44;
printk_debug("setting reg. 4a to 0x%x\n", enables);
pci_write_config_byte(dev, 0x4a, enables);
}
// set up the serial port interrupts.
// com2 to 3, com1 to 4
pcibios_write_config_byte(0, devfn, 0x52, 0x34);
if (dev) {
pci_write_config_byte(dev, 0x52, 0x34);
}
dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
if (!dev) {
if(dev0)
{
dev=&dev_cpy;
dev_cpy.devfn|=1;
}
}
if (!dev) {
printk_debug("IDE pci_find_device function 1 failed\n");
}
else {
pci_read_config_byte(dev, 0x40, &enables);
printk_debug("IDE enable in reg.1-40 is 0x%x\n", enables);
enables = 3; // Primary and secondary channel enable
printk_debug("set IDE reg.1-40 to 0x%x\n", enables);
pci_write_config_byte(dev, 0x40, enables);
pci_read_config_byte(dev, 0x40, &enables);
printk_debug("IDE enable in reg.1-40 read back is 0x%x\n", enables);
}
devfn = PCI_DEVFN(7, 1);
pcibios_read_config_byte(0, devfn, 0x40, &enables);
printk_debug("enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pcibios_write_config_byte(0, devfn, 0x40, enables);
pcibios_read_config_byte(0, devfn, 0x40, &enables);
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
// address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
pcibios_read_config_byte(0, devfn, 0x9, &enables);
printk_debug("enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
enables &= ~0xf;
// cf/cg silicon needs an 'f' here.
enables |= 0xf;
pcibios_write_config_byte(0, devfn, 0x9, enables);
pcibios_read_config_byte(0, devfn, 0x9, &enables);
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
if (dev) {
pci_read_config_byte(dev, 0x9, &enables);
printk_debug("enables in reg 0x9 0x%x\n", enables);
// standard bios sets master bit.
pcibios_read_config_byte(0, devfn, 0x4, &enables);
printk_debug("command in reg 0x4 0x%x\n", enables);
enables |= 5;
pcibios_write_config_byte(0, devfn, 0x4, enables);
pcibios_read_config_byte(0, devfn, 0x4, &enables);
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
enables &= ~0xf;
// cf/cg silicon needs an 'f' here.
enables |= 0x0a;
pci_write_config_byte(dev, 0x9, enables);
pci_read_config_byte(dev, 0x09, &enables);
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
pci_read_config_byte(dev, 0x4, &enables);
printk_debug("command in reg 0x4 0x%x\n", enables);
enables |= 5;
pci_write_config_byte(dev, 0x4, enables);
pci_read_config_byte(dev, 0x4, &enables);
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
// oh well, the PCI BARs don't work right.
// This chip will not work unless IDE runs at standard legacy
// values.
pcibios_write_config_dword(0, devfn, 0x10, 0x1f1);
pcibios_write_config_dword(0, devfn, 0x14, 0x3f5);
pcibios_write_config_dword(0, devfn, 0x18, 0x171);
pcibios_write_config_dword(0, devfn, 0x1c, 0x375);
pcibios_write_config_dword(0, devfn, 0x20, 0xcc0);
pci_write_config_dword(dev, 0x10, 0x1f1);
pci_write_config_dword(dev, 0x14, 0x3f5);
pci_write_config_dword(dev, 0x18, 0x171);
pci_write_config_dword(dev, 0x1c, 0x375);
pci_write_config_dword(dev, 0x20, 0xcc1);
}
}

2
src/superio/winbond/w83627hf/setup_serial.inc
View file

@ -49,7 +49,7 @@
#if defined(SIO_SYSTEM_CLK_INPUT)
/* Setup up the clock input */
SIO_WRITE_CONFIG(0x84 | SIO_SYSTEM_CLK_INPUT), 0x24)
SIO_WRITE_CONFIG((0x84 | SIO_SYSTEM_CLK_INPUT), 0x24)
#endif
/* enable serial 1 */
SIO_SET_LOGICAL_DEVICE(SIO_COM1_DEVICE)