Initial checkin for supermicro p4dc6

This also includes a bunch of my pending work including
- Updated serial code so we can compile in different serial port speeds
- Updates to the build system so that:
  - Makefile.settings holds all of the settings of the config variables
  - ldoptions and cpuflags are generated automatically with perl scripts
  - src/config/Config holds all of the architecture neutral make file settings
- Initial work on the P4 including how to use cache as ram
- Update to the ioapic code for the P4 because it delivers irqs on the system
  bus instead of an out of band bus
- Updated version of printf that doesn't need an intermediate buffer
  - logbuf_subr now handles the case when we want to use a log buffer
- video_subr handles the preliminary code for writing to a video device.
- Pending changes for the L440GX are merged in as well (hopefully I haven't
  messed then up since they were written).

src/arch/alpha/config/make.base

@@ -1,42 +1,19 @@
 biosbase 0
 rambase 0x8000
-makedefine CC:=gcc
-makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
-makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
-makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall
+
+option USE_DEFAULT_LAYOUT=1
+ldscript arch/alpha/config/ldscript.base USE_DEFAULT_LAYOUT
+
 makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a
 makerule all : linuxbios.rom ;
 makerule linuxbios.rom: linuxbios.strip makerom ; ./makerom -l0x310000 -i7 -v linuxbios.strip -o linuxbios.rom
-makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
-makerule linuxbios: linuxbios.a ; @rm -f biosobject
-makerule etags: $(SOURCES) ; etags $(SOURCES)
-makerule tags: $(SOURCES) ; ctags $(SOURCES)
-makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config 
-addaction linuxbios $(LINK) 
-addaction linuxbios nm -n linuxbios > linuxbios.map
 
-makerule ldscript.ld : ldscript.options $(LDSUBSCRIPTS-1) ; echo "INCLUDE ldscript.options" > ldscript.ld ; for file in $(LDSUBSCRIPTS-1) ; do echo "INCLUDE $$file" >> ldscript.ld ; done
 
-makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a
-addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1)
-
-makerule crt0.s: crt0.S ; $(CC) $(CPPFLAGS) -I$(TOP)/src -E $< > crt0.s
-
-makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s
 #makerule makerom: $(TOP)/util/makerom/makerom.c $(TOP)/util/makerom/compress.c ; $(CC) -o makerom $(TOP)/util/makerom/makerom.c $(TOP)/util/makerom/compress.c
 
-makerule clean : ; rm -f  linuxbios.* *.o mkrom xa? *~
-addaction clean rm -f linuxbios crt0.s
-addaction clean rm -f a.out *.s *.l
-addaction clean rm -f TAGS tags
-addaction clean rm -f docipl
-
+addaction clean rm -f makerom
 
 # do standard config files that the user need not specify
 # for now, this is just 'lib', but it may be more later. 
 dir /src/arch/alpha
-dir /src/lib
-dir /src/boot
-dir /src/rom
 dir /util/makerom

src/arch/i386/config/crt0.base

@@ -26,9 +26,9 @@
 
 CRT0_PARAMETERS
 
-#if defined(SERIAL_CONSOLE) && defined(DEBUG)
+#if defined(SERIAL_CONSOLE) && (DEFAULT_CONSOLE_LOGLEVEL >= 7)
         TTYS0_TX_STRING($str_after_ram)
-#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */
+#endif 
 
 	/* clear boot_complete flag */
 	xorl	%ebp, %ebp
@@ -96,10 +96,9 @@ __main:
 	 */ 
 	intel_chip_post_macro(0xfe)	/* post fe */
 
-#if defined(SERIAL_CONSOLE) && defined(DEBUG)
+#if defined(SERIAL_CONSOLE) && (DEFAULT_CONSOLE_LOGLEVEL >= 7)
         TTYS0_TX_STRING($str_pre_main)
-#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */
-
+#endif 
 
 	/* memory is up. Let\'s do the rest in C -- much easier. */
 

src/arch/i386/config/make.base

@@ -6,63 +6,43 @@ option ROM_IMAGE_SIZE=65536
 option MAX_CPUS=1
 # Reserve 256K for the heap
 option HEAP_SIZE=0x40000
-# Reserve 64K for each stack
-option STACK_SIZE=0x10000
+# Reserve 8K for each stack
+option STACK_SIZE=0x2000
 
 # By default on x86 we have a memory hole between 640K and 1MB
 option MEMORY_HOLE=1
 
-makedefine CC:=gcc 
-makedefine CPP:= gcc -x assembler-with-cpp -DASSEMBLY -E
-makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
-makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
-makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall
+option USE_DEFAULT_LAYOUT=1
+ldscript arch/i386/config/ldscript.base USE_DEFAULT_LAYOUT
+ldscript arch/i386/config/ldscript.cacheram USE_CACHE_RAM
+
+# How do I add -mprefered-stack-boundary=2 if the compiler supports it?
+# On x86 tt results in a code size reduction.
+#
+
+dir /src/config
+
 makerule all : romimage ;
 makerule floppy : all ; mcopy -o romimage a:
 makerule romimage : linuxbios.rom vmlinux.bin.gz.block ; cat vmlinux.bin.gz.block linuxbios.rom > romimage
 
+
 makerule linuxbios.rom: linuxbios.strip ; 
 addaction linuxbios.rom export size=`ls -l linuxbios.strip | (read p c u g size r ; echo $$size)` ; \
 addaction linuxbios.rom echo $$size ; \
 addaction linuxbios.rom dd if=linuxbios.strip of=linuxbios.rom bs=1 seek=`expr $(ROM_IMAGE_SIZE) - $$size`
 
-makerule linuxbios.strip: linuxbios ; objcopy -O binary linuxbios linuxbios.strip
 
-makerule linuxbios.o : crt0.o linuxbios.a $(LIBGCC_FILE_NAME)  ; $(CC) -nostdlib -r -o $@ crt0.o linuxbios.a $(LIBGCC_FILE_NAME)
-
-makerule ldscript.ld : ldoptions $(LDSUBSCRIPTS-1) ; echo "INCLUDE ldoptions" > ldscript.ld ; for file in $(LDSUBSCRIPTS-1) ; do echo "INCLUDE $$file" >> ldscript.ld ; done
-
-makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o 
-addaction linuxbios nm -n linuxbios > linuxbios.map
-
-makerule etags: $(SOURCES) ; etags $(SOURCES)
-makerule tags: $(SOURCES) ; ctags $(SOURCES)
-makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config 
-
-makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a
-addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1)
-
-makerule crt0.s: crt0.S ; $(CPP) $(CPPFLAGS) -I$(TOP)/src $< > crt0.s
-
-makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s
 makerule mkrom: $(TOP)/mkrom/mkrom.c ; $(CC) -o mkrom $<
 
-makerule clean : ; rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~
-addaction clean rm -f linuxbios romimage crt0.s
-addaction clean rm -f a.out *.s *.l
-addaction clean rm -f TAGS tags
-addaction clean rm -f docipl
-
 
 makerule vmlinux.bin.gz.block : vmlinux.bin.gz ; dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
 makerule vmlinux.bin.gz: vmlinux.bin ;gzip -f -3 vmlinux.bin
 makerule vmlinux.bin: $(LINUX)/vmlinux ;  objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
 
 
+addaction clean rm -f romimage mkrom vmlinux.*
+
 # do standard config files that the user need not specify
 # for now, this is just 'lib', but it may be more later. 
 dir /src/arch/i386
-dir /src/lib
-dir /src/boot
-dir /src/rom

src/arch/i386/lib/Config

@@ -1,4 +1,4 @@
 object i386_subr.o
 object params.o
 object hardwaremain.o
-object pirq_routing.o
+object pirq_routing.o HAVE_PIRQ_TABLE

src/arch/i386/lib/i386_subr.c

@@ -9,6 +9,10 @@
 #include <string.h>
 #include <arch/i386_subr.h>
 
+#if defined(SMP) || defined(IOAPIC)
+#define APIC 1
+#endif
+
 void cache_on(unsigned long totalram)
 {
 	post_code(0x60);
@@ -45,7 +49,7 @@ void interrupts_on()
 	 * see the Intel mp1.4 spec, page A-3
 	 */
 
-#if defined(SMP)
+#if defined(APIC)
 	/* Only Pentium Pro and later have those MSR stuff */
 	unsigned long low, high;
 
@@ -81,7 +85,7 @@ void interrupts_on()
 		| (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING | 
 			APIC_DELIVERY_MODE_NMI)
 		);
-#else /* SMP */
+#else /* APIC */
 #ifdef i686
 	/* Only Pentium Pro and later have those MSR stuff */
 	unsigned long low, high;
@@ -92,7 +96,7 @@ void interrupts_on()
 	low &= ~APIC_BASE_MSR_ENABLE;
 	wrmsr(APIC_BASE_MSR, low, high);
 #endif /* i686 */
-#endif /* SMP */
+#endif /* APIC */
 	printk_info("done.\n");
 	post_code(0x9b);
 }

src/arch/i386/lib/pirq_routing.c

@@ -1,4 +1,3 @@
-#ifdef HAVE_PIRQ_TABLE
 #include <printk.h>
 #include <pci.h>
 #include <arch/pirq_routing.h>
@@ -61,5 +60,3 @@ void copy_pirq_routing_table(void)
 	memcpy((char *) RTABLE_DEST, &intel_irq_routing_table, intel_irq_routing_table.size);
 	printk_info("done.\n");
 }
-#endif /* HAVE_PIRQ_TABLE */
-

src/arch/i386/lib/set_memory_size_noop.inc

@@ -0,0 +1,6 @@
+jmp	set_memory_size_out
+
+set_memory_size:
+	RETSP
+
+set_memory_size_out:

src/arch/i386/smp/ioapic.c

@@ -24,61 +24,6 @@ struct ioapicreg ioapicregvalues[] = {
 #define NMI		(4 << 8)
 #define SMI		(2 << 8)
 #define INT		(1 << 8)
-#if 0 /* L440GX */
-	{0x00, DISABLED, NONE},
-	{0x01, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x59, ALL},
-	{0x02, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x51, ALL},
-	{0x03, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x61, NONE},
-	{0x04, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x69, ALL},
-	{0x05, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x71, NONE},
-	{0x06, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x79, NONE},
-	{0x07, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x81, NONE},
-	{0x08, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x89, ALL},
-	{0x09, DISABLED, NONE},
-	{0x0a, DISABLED, NONE},
-	{0x0b, DISABLED, NONE},
-	{0x0c, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x91, ALL},
-	{0x0d, DISABLED, NONE},
-	{0x0e, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x99, ALL},
-	{0x0f, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xa1, ALL},
-	{0x10, DISABLED, NONE},
-	{0x11, DISABLED, NONE},
-	{0x12, DISABLED, NONE},
-	{0x13, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0xa9, ALL},
-	{0x14, DISABLED, NONE},
-	{0x15, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0xb1, ALL},
-	{0x16, DISABLED, NONE},
-	{0x17, DISABLED, NONE}
-#endif
-#if 0 /* tyan guinness */
-	/* mask, trigger, polarity, destination, delivery, vector */
-	{0x00, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|ExtINT|0x0,	ALL},
-	{0x01, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x1,		ALL},
-	{0x02, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x0,		ALL},
-	{0x03, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x3,		ALL},
-	{0x04, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x4,		ALL},
-	{0x05, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x5,		ALL},
-	{0x06, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x6,		ALL},
-	{0x07, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x7,		ALL},
-	{0x08, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x8,		ALL},
-	{0x09, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x9,		ALL},
-	{0x0a, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xa,		ALL},
-	{0x0b, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xb,		ALL},
-	{0x0c, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xc,		ALL},
-	{0x0d, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xd,		ALL},
-	{0x0e, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xe,		ALL},
-	{0x0f, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xf,		ALL},
-	{0x10, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x10,	ALL},
-	{0x11, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x11,	ALL},
-	{0x12, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x12,	ALL},
-	{0x13, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x13,	ALL},
-	{0x14, DISABLED, NONE},
-	{0x14, DISABLED, NONE},
-	{0x15, DISABLED, NONE},
-	{0x16, DISABLED, NONE},
-	{0x17, DISABLED, NONE},
-#endif
-#if 1
 	/* mask, trigger, polarity, destination, delivery, vector */
 	{0x00, DISABLED, NONE},
 	{0x01, DISABLED, NONE},
@@ -105,7 +50,6 @@ struct ioapicreg ioapicregvalues[] = {
 	{0x15, DISABLED, NONE},
 	{0x16, DISABLED, NONE},
 	{0x17, DISABLED, NONE},
-#endif
 };
 
 void setup_ioapic(void)
@@ -117,6 +61,13 @@ void setup_ioapic(void)
 	struct ioapicreg *a = ioapicregvalues;
 
 	l = (unsigned long *) nvram;
+#if defined(i786)
+	/* For the pentium 4 and above apic deliver their interrupts
+	 * on the front side bus, enable that.
+	 */
+	l[0] = 0x03;
+	l[4] = 1;
+#endif /* i786 */
 	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
 	     i++, a++) {
 		l[0] = (a->reg * 2) + 0x10;

src/config/Config

@@ -0,0 +1,47 @@
+## This is Architecture independant part of the makefile
+
+makedefine CC:=gcc 
+makedefine CPP:= gcc -x assembler-with-cpp -DASSEMBLY -E
+makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
+makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
+
+makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
+makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin  -Wall
+
+makerule ldscript.ld : ldoptions $(LDSUBSCRIPTS-1) ; echo "INCLUDE ldoptions" > $@ ; for file in $(LDSUBSCRIPTS-1) ; do echo "INCLUDE $$file" >> $@ ; done
+
+makerule cpuflags : Makefile.settings ; perl -e 'print "CPUFLAGS :=\n"; foreach $$var (split(" ", $$ENV{VARIABLES})) { if (exists($$ENV{$$var})) { print "CPUFLAGS += -D$$var" . (length($$ENV{$$var})?"=\x27$$ENV{$$var}\x27":"") ."\n"} else { print "CPUFLAGS += -U$$var\n"} }' > $@
+
+makerule ldoptions : Makefile.settings ; perl -e 'foreach $$var (split(" ", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print "$$var = $$ENV{$$var};\n"; }}' > $@
+
+makerule linuxbios.strip: linuxbios ; objcopy -O binary linuxbios linuxbios.strip
+
+makerule linuxbios.o : crt0.o linuxbios.a $(LIBGCC_FILE_NAME)  ; $(CC) -nostdlib -r -o $@ crt0.o linuxbios.a $(LIBGCC_FILE_NAME)
+
+
+makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o 
+addaction linuxbios nm -n linuxbios > linuxbios.map
+
+makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a
+addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1)
+
+makerule crt0.s: crt0.S ; $(CPP) $(CPPFLAGS) -I$(TOP)/src $< > crt0.s
+
+makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s
+
+makerule etags: $(SOURCES) ; etags $(SOURCES)
+makerule tags: $(SOURCES) ; ctags $(SOURCES)
+makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config 
+
+makerule clean : ; rm -f linuxbios.* *~
+addaction clean rm -f linuxbios 
+addaction clean rm -f ldoptions cpuflags ldscript.ld
+addaction clean rm -f a.out *.s *.l *.o
+addaction clean rm -f TAGS tags
+addaction clean rm -f docipl
+
+# do standard config files that the user need not specify
+# for now, this is just 'lib', but it may be more later. 
+dir /src/lib
+dir /src/boot
+dir /src/rom

src/cpu/i386/entry16.inc

@@ -36,6 +36,10 @@ EXT(_start): jmp _realstart
  * at 0x18; these are Linux-compatible. 
  */
 
+#ifndef CACHE_RAM_BASE
+#define CACHE_RAM_BASE 0
+#endif
+
 /** GDT. we have modified this from the original freebios to make it 
  * compatible with linux. This puts text at seg 0x10 and data at 0x18
  */
@@ -46,16 +50,16 @@ EXT(gdtptr):
 	.long	gdt		/* we know the offset */
 gdt:
 	.word	0x0000, 0x0000		/* dummy */
-	.byte	0x0, 0x0, 0x0, 0x0
-	
-	.word	0x0000, 0x0000		/* dummy */
-	.byte	0x0, 0x0, 0x0, 0x0
+	.byte	0x00, 0x00, 0x00, 0x00
+
+	.word	0xffff, (CACHE_RAM_BASE & 0xffff)		/* flat offset data segment */
+	.byte	((CACHE_RAM_BASE >> 16)& 0xff), 0x93, 0xcf, ((CACHE_RAM_BASE >> 24) & 0xff)
 	
 	.word	0xffff, 0x0000		/* flat code segment */
-	.byte	0x0, 0x9b, 0xcf, 0x0	
+	.byte	0x00, 0x9b, 0xcf, 0x00	
 	
 	.word	0xffff, 0x0000		/* flat data segment */
-	.byte	0x0, 0x93, 0xcf, 0x0	
+	.byte	0x00, 0x93, 0xcf, 0x00	
 
 
 _realstart:

src/cpu/i786/Config

@@ -0,0 +1 @@
+option i786

src/cpu/i786/cache_ram_fini.inc

@@ -0,0 +1,39 @@
+#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE)
+	/* Note:  We cannot be running from simulated ram in
+	 * this code.  If we are evil things will happen.
+	 */
+
+	/* Disable the cache */
+	movl	%cr0, %eax
+	orl	$0x40000000, %eax
+	movl	%eax, %cr0
+
+	/* Flush everything that is left in the cache,
+	 * We don't want random writes to memory to occur later on.
+	 */
+	invd
+
+	/* Disable the cache ram mtrr */
+	movl	$0x204, %ecx
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	movl	$0x205, %ecx
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Reenable the cache now that the mtrr is cleared */
+	movl	%cr0, %eax
+	andl	$0x9fffffff, %eax
+	movl	%eax, %cr0
+
+	/* Reload the normal data segments */
+	movw	$0x18, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+	movw	%ax, %fs
+	movw	%ax, %gs
+#endif

src/cpu/i786/cache_ram_init.inc

@@ -0,0 +1,42 @@
+#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE)
+	/* Disable the cache while we set up the cache ram MTRR */
+	movl	%cr0, %eax
+	orl	$0x40000000, %eax
+	movl	%eax, %cr0
+
+	/* Set up an mtrr in write-back mode over some arbitrary
+	 * location.  As long as we do not get a capacity miss,
+	 * or a multiprocessor conflict miss this should allow us to
+	 * function as if we have memory even when it hasn't been
+	 * enabled yet.
+	 */
+	movl	$0x204, %ecx		/* mtrr[0] physical base register */
+	xorl	%edx, %edx
+	movl	$(CACHE_RAM_BASE | 0x006), %eax
+	wrmsr
+
+	movl	$0x205, %ecx		/* mtrr[0] physical mask register */
+	movl	$0x0000000f, %edx
+	movl	$(~(CACHE_RAM_SIZE - 1) | 0x800), %eax
+	wrmsr
+
+	/* Reenable the cache now that the mtrr is set up */
+	movl	%cr0, %eax
+	andl	$0x9fffffff, %eax
+	movl	%eax, %cr0
+
+	/* Force cache ram area into cache */
+	movl	$CACHE_RAM_BASE, %esi
+	movl	$(CACHE_RAM_BASE + CACHE_RAM_SIZE), %edi
+1:	movl	(%esi), %eax
+	addl	$4, %esi
+	movl	%eax, (%esi)
+	cmpl	%esi, %edi
+	jnz	1b
+
+	/* Load a different set of data segments */
+	movw	$0x08, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+#endif

src/cpu/i786/cache_ram_start.inc

@@ -0,0 +1,25 @@
+	/* copy data segment from FLASH ROM to CACHE */
+	movl	$(EXT(_ldata) - CACHE_RAM_BASE), %esi
+	movl	$EXT(_data), %edi
+	movl	$(EXT(_eldata) - CACHE_RAM_BASE), %ecx
+	subl	%esi, %ecx
+	jz	1f			/* should not happen */
+	rep
+	movsb
+1:
+
+	/** clear bss */
+	movl	$EXT(_bss), %edi
+	movl	$EXT(_ebss), %ecx
+	subl	%edi, %ecx
+	jz	1f
+	xorl	%eax, %eax
+	rep
+	stosb
+1:
+
+	/* set new stack */
+	movl	$(_stack + STACK_SIZE), %esp
+
+	call	cache_ram_start
+

src/cpu/i786/earlymtrr.inc

@@ -0,0 +1,108 @@
+#include <cpu/p6/mtrr.h>
+
+/* The fixed and variable MTRRs are powered-up with random values, clear them to
+ * MTRR_TYPE_UNCACHABLE for safty reason 
+ */
+
+earlymtrr_start:
+	xorl	%eax, %eax			# clear %eax and %edx
+	xorl	%edx, %edx			#
+	movl	$fixed_mtrr_msr, %esi
+
+clear_fixed_var_mtrr:
+	lodsl	(%esi), %eax
+	testl	%eax, %eax
+	jz	clear_fixed_var_mtrr_out
+
+	movl	%eax, %ecx
+	xorl	%eax, %eax
+	wrmsr
+
+	jmp	clear_fixed_var_mtrr
+clear_fixed_var_mtrr_out:
+
+#ifdef MEMORY_HOLE
+set_fixed_mtrr:
+	/* enable Write Back Cache for 0-640KB */
+	movl	$MTRRfix64K_00000_MSR, %ecx
+	rdmsr
+	movl	$0x06060606, %edx
+	movl	$0x06060606, %eax
+	wrmsr
+
+	movl	$MTRRfix16K_80000_MSR, %ecx
+	rdmsr
+	movl	$0x06060606, %edx
+	movl	$0x06060606, %eax
+	wrmsr
+#endif /* MEMORY_HOLE */
+
+set_var_mtrr:
+#if 0
+	/* enable caching for 0 - 128MB using variable mtrr */
+	movl	$0x200, %ecx
+	rdmsr
+	andl	$0xfffffff0, %edx
+	orl	$0x00000000, %edx
+	andl	$0x00000f00, %eax
+	orl	$0x00000006, %eax
+	wrmsr
+
+	movl	$0x201, %ecx
+	rdmsr
+	andl	$0xfffffff0, %edx
+	orl	$0x0000000f, %edx
+	andl	$0x000007ff, %eax
+	orl	$0xf0000800, %eax
+	wrmsr
+#endif
+
+#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+	/* enable write protect caching so we can do execute in place
+	 * on the flash rom.
+	 */
+	movl	$0x202, %ecx
+	xorl	%edx, %edx
+	movl	$(XIP_ROM_BASE | 0x005), %eax
+	wrmsr	
+
+	movl	$0x203, %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+	wrmsr
+#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+
+enable_mtrr:	
+	/* Set the default memory type and enable fixed and variable MTRRs */
+	movl	$0x2ff, %ecx
+	xorl	%edx, %edx
+#ifdef MEMORY_HOLE
+	/* Enable Fixed and Variable MTRRs */
+	movl	$0x00000c00, %eax
+#else
+	/* Enable Variable MTRRs */
+	movl	$0x00000800, %eax
+#endif /* MEMORY_HOLE */
+	wrmsr
+
+
+	/* enable cache */
+	movl	%cr0, %eax
+	andl	$0x9fffffff,%eax
+	movl	%eax, %cr0
+
+	jmp	earlymtrr_end
+
+fixed_mtrr_msr:	
+	.long	0x250, 0x258, 0x259
+	.long	0x268, 0x269, 0x26A
+	.long	0x26B, 0x26C, 0x26D
+	.long	0x26E, 0x26F
+var_mtrr_msr:
+	.long	0x200, 0x201, 0x202, 0x203
+	.long	0x204, 0x205, 0x206, 0x207
+	.long	0x208, 0x209, 0x20A, 0x20B
+	.long	0x20C, 0x20D, 0x20E, 0x20F
+	.long	0x000 /* NULL, end of table */
+	
+earlymtrr_end:

src/cpu/p6/mtrr.c

@@ -109,6 +109,7 @@ static unsigned char fixed_mtrr_values[][4] = {
 	{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
 };
 #else
+
 static unsigned char fixed_mtrr_values[][4] = {
 	/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
 	{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
@@ -143,6 +144,7 @@ static unsigned char fixed_mtrr_values[][4] = {
 	/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
 	{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
 };
+
 #endif
 
 #undef FB

src/include/logbuf_subr.h

@@ -0,0 +1,4 @@
+#ifndef LOGBUF_SUBR_H
+#define LOGBUF_SUBR_H
+
+#endif /* LOGBUF_SUBR_H */

src/include/pci_ids.h

@@ -1205,6 +1205,15 @@
 #define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
 #define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
 #define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
+
+#define PCI_DEVICE_ID_INTEL_82801BA_1E0	0x244e
+#define PCI_DEVICE_ID_INTEL_82801BA_1F0	0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_1F1	0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_1F2	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BA_1F3	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_1F4	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BA_1F5	0x2445
+
 #define PCI_DEVICE_ID_INTEL_82820FW_0	0x2440
 #define PCI_DEVICE_ID_INTEL_82820FW_1	0x2442
 #define PCI_DEVICE_ID_INTEL_82820FW_2	0x2443

src/include/subr.h

@@ -5,6 +5,9 @@
 
 void displayinit(void);
 void display(char msg[]);
+void display_tx_byte(unsigned char byte);
+void display_tx_break(void);
+
 void error(char errmsg[]);
 void post_code(uint8_t value);
 

src/include/video_subr.h

@@ -0,0 +1,7 @@
+#ifndef VIDEO_SUBR_H
+#define VIDEO_SUBR_H
+
+void video_init(void);
+void video_tx_byte(unsigned char byte);
+
+#endif /* VIDEO_SUBR_H */

src/lib/Config

@@ -2,7 +2,9 @@ object linuxbiosmain.o
 object linuxpci.o
 object newpci.o
 object printk.o
-object serial_subr.o
+object serial_subr.o SERIAL_CONSOLE
+object video_subr.o VIDEO_CONSOLE
+object logbuf_subr.o LOGBUF_CONSOLE
 object subr.o
 object vsprintf.o
 object memset.o

src/lib/logbuf_subr.c

@@ -0,0 +1,14 @@
+#include <logbuf_subr.h>
+
+#define LOGBUF_SIZE = 1024;
+
+// KEEP THIS GLOBAL. 
+// I need the address so I can watch it with the ARIUM hardware. RGM.
+char logbuf[LOGBUF_SIZE];
+int logbuf_offset = 0;
+
+void logbuf_tx_byte(unsigned char byte)
+{
+	logbuf[logbuf_offset] = byte;
+	logbuf_offset = (logbuf_offset +1) % LOGBUF_SIZE;
+}

src/lib/newpci.c

@@ -750,9 +750,9 @@ void enable_resources(struct pci_bus *bus)
 		u16 command;
 		pci_read_config_word(curdev, PCI_COMMAND, &command);
 		command |= curdev->command;
-		pci_write_config_word(curdev, PCI_COMMAND, command);
-		printk_debug("DEV Set command bus 0x%x devfn 0x%x to 0x%x\n",
+		printk_debug("DEV Set command bus 0x%02x devfn 0x%02x to 0x%02x\n",
 		    curdev->bus->number, curdev->devfn, command);
+		pci_write_config_word(curdev, PCI_COMMAND, command);
 	}
 }
 

src/lib/printk.c

@@ -12,12 +12,9 @@ static char rcsid[] = "$Id$";
 //typedef void * va_list;
 
 #include <stdarg.h>
+#include <subr.h>
 #include <smp/spinlock.h>
 
-// KEEP THIS GLOBAL. 
-// I need the address so I can watch it with the ARIUM hardware. RGM.
-char log_buf[1024];
-
 /* printk's without a loglevel use this.. */
 #define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */
 
@@ -36,7 +33,7 @@ int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL;
 int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
 
 void display(char*);
-extern int vsprintf(char *buf, const char *, va_list);
+extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
 
 spinlock_t console_lock = SPIN_LOCK_UNLOCKED;
 
@@ -52,10 +49,10 @@ int do_printk(int msg_level, const char *fmt, ...)
 	spin_lock(&console_lock);
 
 	va_start(args, fmt);
-	i = vsprintf(log_buf, fmt, args); /* hopefully i < sizeof(log_buf)-4 */
+	i = vtxprintf(display_tx_byte, fmt, args);
 	va_end(args);
 
-	display(log_buf);
+	display_tx_break();
 
 	spin_unlock(&console_lock);
 

src/lib/serial_subr.c

@@ -18,6 +18,14 @@ static char rcsid[] = "$Id$";
 
 #define TTYS0_DIV	(115200/TTYS0_BAUD)
 
+/* Line Control Settings */
+#ifndef TTYS0_LCS
+/* Set 8bit, 1 stop bit, no parity */
+#define TTYS0_LCS	0x3
+#endif
+
+#define UART_LCS	TTYS0_LCS
+
 /* Data */
 #define UART_RBR 0x00
 #define UART_TBR 0x00
@@ -36,10 +44,6 @@ static char rcsid[] = "$Id$";
 #define UART_MSR 0x06
 #define UART_SCR 0x07
 
-#ifndef TTYS0_BAUD
-#define TTYS0_BAUD 115200
-#endif
-
 static inline int uart_can_tx_byte(unsigned base_port)
 {
 	return inb(base_port + UART_LSR) & 0x20;
@@ -141,10 +145,10 @@ inline void uart_init(unsigned base_port, unsigned divisor)
 	/* enable fifo's */
 	outb(0x01, base_port + UART_FCR);
 	/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
-	outb(0x83, base_port + UART_LCR);
+	outb(0x80 | UART_LCS, base_port + UART_LCR);
 	outb(divisor & 0xFF,   base_port + UART_DLL);
 	outb((divisor >> 8) & 0xFF,    base_port + UART_DLM);
-	outb(0x03, base_port + UART_LCR);
+	outb(UART_LCS, base_port + UART_LCR);
 }
 
 void ttys0_init(void)

src/lib/subr.c

@@ -18,63 +18,18 @@ static char rcsid[] = "$Id$";
 #ifdef SERIAL_CONSOLE
 #include <serial_subr.h>
 #endif
+#ifdef VIDEO_CONSOLE
+#include <video_subr.h>
+#endif
+#ifdef LOGBUF_CONSOLE
+#include <logbuf_subr.h>
+#endif
 
-#ifdef VIDEO_BIOS_WORKS
-
-# error the video display code has not been tested
-
-// kludgy but this is only used here ...
-static char *vidmem;		/* The video buffer, should be replaced by symbol in ldscript.ld */
-static int video_line, video_col;
-
-#define LINES  	25		/* Number of lines and   */
-#define COLS   	80		/*   columns on display  */
-#define VIDBUFFER 0x20000;
-
-static void video_init(void)
-{
-	video_line = 0;
-	video_col = 0;
-	vidmem = (char *) VIDBUFFER;
-	memset(vidmem, 0, 64*1024);
-}
-static void video_scroll(void)
-{
-	int i;
-
-	memcpy(vidmem, vidmem + COLS * 2, (LINES - 1) * COLS * 2);
-	for (i = (LINES - 1) * COLS * 2; i < LINES * COLS * 2; i += 2)
-		vidmem[i] = ' ';
-}
-
-static void video_tx_byte(unsigned char byte)
-{
-	if (byte == '\n') {
-		video_line++;
-	}
-	else if (byte == '\r') {
-		video_col = 0;
-	}
-	else {
-		videmem[((video_col + (video_line *COLS)) * 2)] = byte;
-		videmem[((video_col + (video_line *COLS)) * 2) +1] = 0x07;
-		video_col++;
-	}
-	if (video_col >= COLS) {
-		video_line++;
-		video_col = 0;
-	}
-	if (video_line >= LINES) {
-		video_scroll();
-		video_line--;
-	}
-}
-#endif /* VIDEO_BIOS_WORKS */
 
 // initialize the display
 void displayinit(void)
 {
-#ifdef VIDEO_BIOS_WORKS
+#ifdef VIDEO_CONSOLE
 	video_init();
 #endif
 #ifdef SERIAL_CONSOLE
@@ -82,9 +37,9 @@ void displayinit(void)
 #endif
 }
 
-void display_tx_byte(unsigned char byte)
+static void __display_tx_byte(unsigned char byte)
 {
-#ifdef VIDEO_BIOS_WORKS
+#ifdef VIDEO_CONSOLE
 	video_tx_byte(byte);
 #endif
 #ifdef SERIAL_CONSOLE
@@ -93,17 +48,29 @@ void display_tx_byte(unsigned char byte)
 #ifdef SROM_CONSOLE
 	srom_tx_byte(byte);
 #endif
+#ifdef LOGBUF_CONSOLE
+	logbuf_tx_byte(byte);
+#endif
+}
+
+void display_tx_break(void)
+{
+}
+
+void display_tx_byte(unsigned char byte)
+{
+	if (byte == '\n')
+		__display_tx_byte('\r');
+	__display_tx_byte(byte);
 }
 
 void display(char *string)
 {
 	while(*string) {
-		if (*string == '\n') {
-			display_tx_byte('\r');
-		}
 		display_tx_byte(*string);
 		string++;
 	}
+	display_tx_break();
 }
 
 void error(char errmsg[])

src/lib/video_subr.c

@@ -0,0 +1,49 @@
+#include <video_subr.h>
+# error the video display code has not been tested
+
+// kludgy but this is only used here ...
+static char *vidmem;		/* The video buffer, should be replaced by symbol in ldscript.ld */
+static int video_line, video_col;
+
+#define LINES  	25		/* Number of lines and   */
+#define COLS   	80		/*   columns on display  */
+#define VIDBUFFER 0x20000;
+
+void video_init(void)
+{
+	video_line = 0;
+	video_col = 0;
+	vidmem = (char *) VIDBUFFER;
+	memset(vidmem, 0, 64*1024);
+}
+static void video_scroll(void)
+{
+	int i;
+
+	memcpy(vidmem, vidmem + COLS * 2, (LINES - 1) * COLS * 2);
+	for (i = (LINES - 1) * COLS * 2; i < LINES * COLS * 2; i += 2)
+		vidmem[i] = ' ';
+}
+
+void video_tx_byte(unsigned char byte)
+{
+	if (byte == '\n') {
+		video_line++;
+	}
+	else if (byte == '\r') {
+		video_col = 0;
+	}
+	else {
+		videmem[((video_col + (video_line *COLS)) * 2)] = byte;
+		videmem[((video_col + (video_line *COLS)) * 2) +1] = 0x07;
+		video_col++;
+	}
+	if (video_col >= COLS) {
+		video_line++;
+		video_col = 0;
+	}
+	if (video_line >= LINES) {
+		video_scroll();
+		video_line--;
+	}
+}

src/lib/vsprintf.c

@@ -88,12 +88,13 @@ __res = ((unsigned long) n) % (unsigned) base; \
 n = ((unsigned long) n) / (unsigned) base; \
 __res; })
 
-static char * number(char * str, long num, int base, int size, int precision
+static int number(void (*tx_byte)(unsigned char byte), long num, int base, int size, int precision
 	,int type)
 {
 	char c,sign,tmp[66];
 	const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
 	int i;
+	int count = 0;
 
 	if (type & LARGE)
 		digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
@@ -132,38 +133,35 @@ static char * number(char * str, long num, int base, int size, int precision
 	size -= precision;
 	if (!(type&(ZEROPAD+LEFT)))
 		while(size-->0)
-			*str++ = ' ';
+			tx_byte(' '), count++;
 	if (sign)
-		*str++ = sign;
+		tx_byte(sign), count++;
 	if (type & SPECIAL) {
 		if (base==8)
-			*str++ = '0';
+			tx_byte('0'), count++;
 		else if (base==16) {
-			*str++ = '0';
-			*str++ = digits[33];
+			tx_byte('0'), count++;
+			tx_byte(digits[33]), count++;
 		}
 	}
 	if (!(type & LEFT))
 		while (size-- > 0)
-			*str++ = c;
+			tx_byte(c), count++;
 	while (i < precision--)
-		*str++ = '0';
+		tx_byte('0'), count++;
 	while (i-- > 0)
-		*str++ = tmp[i];
+		tx_byte(tmp[i]), count++;
 	while (size-- > 0)
-		*str++ = ' ';
-	return str;
+		tx_byte(' '), count++;
+	return count;
 }
 
-/* Forward decl. needed for IP address printing stuff... */
-int sprintf(char * buf, const char *fmt, ...);
 
-int vsprintf(char *buf, const char *fmt, va_list args)
+int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args)
 {
 	int len;
 	unsigned long num;
 	int i, base;
-	char * str;
 	const char *s;
 
 	int flags;		/* flags to number() */
@@ -172,10 +170,12 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 	int precision;		/* min. # of digits for integers; max
 				   number of chars for from string */
 	int qualifier;		/* 'h', 'l', or 'L' for integer fields */
+	
+	int count;
 
-	for (str=buf ; *fmt ; ++fmt) {
+	for (count=0; *fmt ; ++fmt) {
 		if (*fmt != '%') {
-			*str++ = *fmt;
+			tx_byte(*fmt), count++;
 			continue;
 		}
 			
@@ -234,10 +234,10 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 		case 'c':
 			if (!(flags & LEFT))
 				while (--field_width > 0)
-					*str++ = ' ';
-			*str++ = (unsigned char) va_arg(args, int);
+					tx_byte(' '), count++;
+			tx_byte((unsigned char) va_arg(args, int)), count++;
 			while (--field_width > 0)
-				*str++ = ' ';
+				tx_byte(' '), count++;
 			continue;
 
 		case 's':
@@ -249,11 +249,11 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 
 			if (!(flags & LEFT))
 				while (len < field_width--)
-					*str++ = ' ';
+					tx_byte(' '), count++;
 			for (i = 0; i < len; ++i)
-				*str++ = *s++;
+				tx_byte(*s++), count++;
 			while (len < field_width--)
-				*str++ = ' ';
+				tx_byte(' '), count++;
 			continue;
 
 		case 'p':
@@ -261,7 +261,7 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 				field_width = 2*sizeof(void *);
 				flags |= ZEROPAD;
 			}
-			str = number(str,
+			count += number(tx_byte,
 				(unsigned long) va_arg(args, void *), 16,
 				field_width, precision, flags);
 			continue;
@@ -270,15 +270,15 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 		case 'n':
 			if (qualifier == 'l') {
 				long * ip = va_arg(args, long *);
-				*ip = (str - buf);
+				*ip = count;
 			} else {
 				int * ip = va_arg(args, int *);
-				*ip = (str - buf);
+				*ip = count;
 			}
 			continue;
 
 		case '%':
-			*str++ = '%';
+			tx_byte('%'), count++;
 			continue;
 
 		/* integer number formats - set up the flags and "break" */
@@ -299,9 +299,9 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 			break;
 
 		default:
-			*str++ = '%';
+			tx_byte('%'), count++;
 			if (*fmt)
-				*str++ = *fmt;
+				tx_byte(*fmt), count++;
 			else
 				--fmt;
 			continue;
@@ -316,10 +316,27 @@ int vsprintf(char *buf, const char *fmt, va_list args)
 			num = va_arg(args, int);
 		else
 			num = va_arg(args, unsigned int);
-		str = number(str, num, base, field_width, precision, flags);
+		count += number(tx_byte, num, base, field_width, precision, flags);
 	}
-	*str = '\0';
-	return str-buf;
+	return count;
+}
+
+/* FIXME this global makes vsprintf non-reentrant
+ */
+static char *str_buf;
+static void str_tx_byte(char byte)
+{
+	*str_buf = byte;
+	str_buf++;
+}
+
+int vsprintf(char * buf, const char *fmt, va_list args)
+{
+	int i;
+	str_buf = buf;
+	i = vtxprintf(str_tx_byte, fmt, args);
+	str_buf = 0;
+	return i;
 }
 
 int sprintf(char * buf, const char *fmt, ...)

src/mainboard/asus/cua/Config

@@ -5,6 +5,7 @@ ldscript cpu/i386/entry16.lds
 mainboardinit northbridge/acer/m1631/chipset_init.inc
 mainboardinit superio/acer/m1535/setup_serial.inc
 mainboardinit pc80/serial.inc
+
 northbridge acer/m1631
 southbridge acer/m1535
 superio acer/m1535

src/mainboard/intel/l440gx/Config

@@ -4,10 +4,12 @@ mainboardinit cpu/i386/entry16.inc
 ldscript cpu/i386/entry16.lds
 mainboardinit cpu/i386/reset16.inc
 ldscript cpu/i386/reset16.lds
+
 mainboardinit northbridge/intel/440gx/reset_test.inc
 
 mainboardinit superio/NSC/pc87309/setup_serial.inc
 mainboardinit pc80/serial.inc
+
 northbridge intel/440gx
 southbridge intel/piix4e
 mainboardinit cpu/p6/earlymtrr.inc

src/mainboard/intel/l440gx/mainboard.c

@@ -28,20 +28,19 @@ void mainboard_fixup()
 	u32 dword;
 	for(i = 0; i < 8; i++) {
 		pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte);
-		printk_debug("DRB[i] = 0x%02x\n", byte);
+		printk_spew("DRB[i] = 0x%02x\n", byte);
 	}
 	pci_read_config_byte(host_bridge_pcidev, 0x57, &byte);
-	printk_debug("DRAMC = 0x%02x\n", byte);
+	printk_spew("DRAMC = 0x%02x\n", byte);
 	pci_read_config_byte(host_bridge_pcidev, 0x74, &byte);
-	printk_debug("RPS = 0x%02x\n", byte);
+	printk_spew("RPS = 0x%02x\n", byte);
 	pci_read_config_word(host_bridge_pcidev, 0x78, &word);
-	printk_debug("PGPOL = 0x%04x\n", word);
+	printk_spew("PGPOL = 0x%04x\n", word);
 	pci_read_config_dword(host_bridge_pcidev, 0x50, &dword);
-	printk_debug("NBXCFG = 0x%04x\n", dword);
+	printk_spew("NBXCFG = 0x%04x\n", dword);
 	}
 	
 #endif
-#if 1
 
 	printk_debug("Reset Control Register\n");
 	outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9);
@@ -157,9 +156,8 @@ void mainboard_fixup()
 	/* DEVRESJ */
 	pci_write_config_dword(pm_pcidev, 0x7c, 0);
 
-#endif
 
-#if 1
+#if 0
 	
 	/* Verify that smi is disabled */
 	printk_debug("Testing SMI\r\n");

src/mainboard/pcchips/m754lmr/Config

@@ -8,6 +8,7 @@ ldscript cpu/i386/entry16.lds
 
 mainboardinit superio/acer/m1535/setup_serial.inc
 mainboardinit pc80/serial.inc
+
 northbridge acer/m1631
 southbridge acer/m1535
 superio acer/m1535

src/mainboard/supermicro/p4dc6/Config

@@ -0,0 +1,73 @@
+arch i386
+mainboardinit cpu/i386/entry16.inc
+ldscript cpu/i386/entry16.lds
+mainboardinit cpu/i386/reset16.inc
+ldscript cpu/i386/reset16.lds
+
+#rambase  0x04000000
+biosbase 0xffff0000
+option XIP_ROM_BASE=0xffff0000
+option XIP_ROM_SIZE=0x10000
+option CACHE_RAM_BASE=0xfff70000
+option CACHE_RAM_SIZE=0x00010000
+option USE_CACHE_RAM=1
+nooption USE_DEFAULT_LAYOUT
+#rambase 0xfff70000
+rambase 0x00000000
+option STACK_SIZE=0x2000
+
+
+#mainboardinit northbridge/amd/amd76x/reset_test.inc
+
+#mainboardinit southbridge/intel/82801/definitions.inc
+#mainboardinit southbridge/intel/82801/disable_watchdog.inc
+#mainboardinit southbridge/intel/82801/lpc_com1.inc
+mainboardinit cpu/i786/earlymtrr.inc
+mainboardinit superio/winbond/w83627hf/setup_serial.inc
+mainboardinit pc80/serial.inc
+#mainboardinit ram/ramtest.inc
+#mainboardinit mainboard/supermicro/p4dc6/spin.inc
+mainboardinit cpu/i786/cache_ram_init.inc
+#mainboardinit mainboard/supermicro/p4dc6/cache_test.inc
+mainboardinit cpu/i786/cache_ram_start.inc
+mainboardinit cpu/i786/cache_ram_fini.inc
+
+northbridge intel/82860
+southbridge intel/82801
+southbridge intel/82806
+
+
+nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1
+
+option RAMTEST=1
+option NO_KEYBOARD
+option ENABLE_FIXED_AND_VARIABLE_MTRRS
+#option FINAL_MAINBOARD_FIXUP
+
+object cacheramtest.o
+object mainboard.o
+object mptable.o HAVE_MP_TABLE
+object irq_tables.o HAVE_PIRQ_TABLE
+#keyboard pc80
+dir ../../../pc80
+
+# FIXME are the SMBUS DIMM locations documented anywhere? 
+option SMBUS_MEM_DEVICE_START=(0xa << 3)
+option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3)
+option SMBUS_MEM_DEVICE_INC=1
+option SIO_BASE=0x2e
+#option SMP=1
+option IOAPIC=1
+option HAVE_MP_TABLE=1
+option HAVE_PIRQ_TABLE=1
+#option MAX_CPUS=2
+#option FINAL_MAINBOARD_FIXUP=1
+#option HAVE_HARD_RESET=1
+#option STACK_SIZE=0x10000
+#option XIP_ROM_SIZE=0x8000
+#option XIP_ROM_BASE=0xffff8000
+nooption MEMORY_HOLE
+
+cpu p5
+cpu p6
+cpu i786

src/mainboard/supermicro/p4dc6/irq_tables.c

@@ -0,0 +1,28 @@
+/* PCI: Interrupt Routing Table found at 0x4011ced0 size = 176 */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	0x52495024, /* u32 signature */
+	0x0100,     /* u16 version   */
+	176,        /* u16 Table size 32+(16*devices) up to 9 devices */
+	0x00,       /* u8 Bus 0 */
+	0xf8,       /* u8 Device 1, Function 0 */
+	0x1c00,     /* u16 reserve IRQ for PCI */
+	0x8086,     /* u16 Vendor */
+	0x7000,     /* Device ID */
+	0x00000000, /* u32 miniport_data */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xb1,   /*  u8 checksum - mod 256 checksum must give zero */
+	{  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
+	    {0x00, 0x10, {{0x62, 0xdeb8}, {0x62, 0xdeb8}, {0x62, 0xdeb8}, {0x62, 0xdeb8}}, 0x01,  0x00},
+	    {0x04, 0x40, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x02,  0x00},
+	    {0x04, 0x38, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x03,  0x00},
+	    {0x04, 0x08, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x04,  0x00},
+	    {0x04, 0x10, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x05,  0x00},
+	    {0x04, 0x18, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x06,  0x00},
+	    {0x04, 0x20, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x07,  0x00},
+	    {0x00, 0xf8, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x6b, 0xdeb8}, {0x63, 0xdeb8}}, 0x00,  0x00},
+	    {0x00, 0x08, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x00,  0x00}
+	}
+};

src/mainboard/supermicro/p4dc6/mainboard.c

@@ -0,0 +1,10 @@
+#include <part/mainboard.h>
+#include <printk.h>
+
+void mainboard_fixup(void)
+{
+	ich2_enable_ioapic();
+	ich2_enable_serial_irqs();
+	printk_notice("Please add a mainboard_fixup!\n");
+	return;
+}

src/mainboard/supermicro/p4dc6/mptable.c

@@ -0,0 +1,106 @@
+#include <arch/smp/mpspec.h>
+#include <string.h>
+#include <printk.h>
+
+void smp_write_config_table(void *v, unsigned long * processor_map)
+{
+	int ioapicid = 0;
+	static const char sig[4] = "PCMP";
+	static const char oem[8] = "LNXI    ";
+	static const char productid[12] = "P4DC6       ";
+	struct mp_config_table *mc;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	memset(mc, 0, sizeof(*mc));
+
+	memcpy(mc->mpc_signature, sig, sizeof(sig));
+	mc->mpc_length = sizeof(*mc); /* initially just the header */
+	mc->mpc_spec = 0x04;
+	mc->mpc_checksum = 0; /* not yet computed */
+	memcpy(mc->mpc_oem, oem, sizeof(oem));
+	memcpy(mc->mpc_productid, productid, sizeof(productid));
+	mc->mpc_oemptr = 0;
+	mc->mpc_oemsize = 0;
+	mc->mpc_entry_count = 0; /* No entries yet... */
+	mc->mpc_lapic = LAPIC_ADDR;
+	mc->mpe_length = 0;
+	mc->mpe_checksum = 0;
+	mc->reserved = 0;
+
+
+	smp_write_processors(mc, processor_map);
+	ioapicid = 2;
+
+	smp_write_bus(mc, 0, "PCI   ");
+	smp_write_bus(mc, 1, "PCI   ");
+	smp_write_bus(mc, 2, "PCI   ");
+	smp_write_bus(mc, 3, "PCI   ");
+	smp_write_bus(mc, 4, "PCI   ");
+	smp_write_bus(mc, 5, "ISA   ");
+	
+	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+
+	
+	/* Onboard ich2 soutbhridge */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+		0x00, (0x1f << 2)|3, 0x02, 0x13);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+		0x00, (0x1f << 2)|2, 0x02, 0x17);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+		0x00, (0x1f << 2)|1, 0x02, 0x11);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+		0x00, (0x1f << 2)|0, 0x02, 0x10);
+
+	/* Onboard PCI NIC */
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+		0x04, (4 <<2)|0, 0x02, 0x10);
+
+	/* ISA backward compatibility interrupts  */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x00, 0x02, 0x00);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x01, 0x02, 0x01);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x00, 0x02, 0x02);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x03, 0x02, 0x03);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x04, 0x02, 0x04);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x06, 0x02, 0x06);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x07, 0x02, 0x07);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
+		0x05, 0x08, 0x02, 0x08);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x09, 0x02, 0x09);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x0d, 0x02, 0x0d);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x0e, 0x02, 0x0e);
+	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x05, 0x0f, 0x02, 0x0f);
+
+	/* Standard local interrupt assignments */
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x00, 0x00, MP_APIC_ALL, 0x00);
+	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+		0x00, 0x00, MP_APIC_ALL, 0x01);
+
+	
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+}
+
+void write_smp_table(void *v, unsigned long *processor_map)
+{
+	smp_write_floating_table(v);
+	smp_write_config_table(v, processor_map);
+}
+
+

src/mainboard/tyan/guiness/mptable.c

@@ -3,7 +3,7 @@
 #include <printk.h>
 #include <cpu/p6/apic.h>
 
-void smp_write_config_table(void *v)
+void smp_write_config_table(void *v, unsigned long * processor_map)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "TYAN    ";
@@ -28,7 +28,7 @@ void smp_write_config_table(void *v)
 	mc->reserved = 0;
 
 
-	smp_write_processors(mc);
+	smp_write_processors(mc, processor_map);
 	smp_write_bus(mc, 0, "PCI   ");
 	smp_write_bus(mc, 1, "PCI   ");
 	smp_write_bus(mc, 2, "ISA   ");
@@ -147,11 +147,11 @@ void smp_write_config_table(void *v)
 		mc, smp_next_mpe_entry(mc));
 }
 
-void write_smp_table(void *v)
+void write_smp_table(void *v, unsigned long *processor_map)
 {
 	printk_debug("Writing the mp table\n");
 	smp_write_floating_table(v);
-	smp_write_config_table(v);
+	smp_write_config_table(v, processor_map);
 }
 
 

src/northbridge/intel/440gx/Config

@@ -1,3 +1,4 @@
+mainboardinit arch/i386/lib/set_memory_size_noop.inc
 mainboardinit northbridge/intel/440gx/raminit.inc
 mainboardinit sdram/generic_sdram_enable.inc
 mainboardinit sdram/generic_sdram.inc

src/northbridge/intel/440gx/reset_test.inc

@@ -1,23 +1,23 @@
-       /* If I have already booted once skip a bunch of initialization */
+	/* If I have already booted once skip a bunch of initialization */
 
 #if 0
-       /* To see if I have already booted I check to see if memory has
-        * been enabled.  In this case by reading the memory size register.
-        * This gets set part way through the memory initialization but
-        * it should be fine for this purpose.
-        */
-       movl    $0x67, %eax
-       PCI_READ_CONFIG_BYTE
-       testb   %al, %al
-       jnz     __cpu_reset
+	/* To see if I have already booted I check to see if memory has
+	 * been enabled.  In this case by reading the memory size register.
+	 * This gets set part way through the memory initialization but
+	 * it should be fine for this purpose.
+	 */
+	movl	$0x67, %eax
+	PCI_READ_CONFIG_BYTE
+	testb	%al, %al
+	jnz	__cpu_reset
 #endif
 #if 1
-       /* To see if I have already booted I check to see if memory has
-        * been enabled.  In this case by seeing if memory refresh
-        * hass ben enabled.
-        */
-       movl    $0x57, %eax
-       PCI_READ_CONFIG_BYTE
-       testb   $0x7, %al
-       jnz     __cpu_reset
+	/* To see if I have already booted I check to see if memory has
+	 * been enabled.  In this case by seeing if memory refresh
+	 * hass ben enabled.
+	 */
+	movl	$0x57, %eax
+	PCI_READ_CONFIG_BYTE
+	testb	$0x7, %al
+	jnz	__cpu_reset
 #endif

src/northbridge/intel/82860/Config

@@ -0,0 +1 @@
+object northbridge.o

src/northbridge/intel/82860/northbridge.c

@@ -0,0 +1,19 @@
+#include <pci.h>
+#include <arch/io.h>
+#include <part/sizeram.h>
+#include <printk.h>
+
+unsigned long sizeram(void)
+{
+	unsigned long size;
+	unsigned short word;
+	
+	printk_notice("\nsizeram!!!\n");
+	/* Read TOM */
+	/* How should we handle > 4GB of ram? */
+	pcibios_read_config_word(0, 0, 0xc4, &word);
+	/* Convert size in 64K bytes to size in K bytes */
+	size = word << 6;
+	return size;
+
+}

src/pc80/serial.inc

@@ -1,24 +1,45 @@
-
 /* Base Address */
-#define TTYS0 0x3f8
+#ifndef TTYS0_BASE
+#define TTYS0_BASE	0x3f8
+#endif
+
+/* Baud Rate */
+#ifndef TTYS0_BAUD
+#define TTYS0_BAUD 115200
+#endif
+
+#if ((115200%TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+
+/* Baud Rate Divisor */
+#define TTYS0_DIV	(115200/TTYS0_BAUD)
+#define TTYS0_DIV_LO	(TTYS0_DIV&0xFF)
+#define TTYS0_DIV_HI	((TTYS0_DIV >> 8)&0xFF)
+
+/* Line Control Settings */
+#ifndef TTYS0_LCS
+/* Set 8bit, 1 stop bit, no parity */
+#define TTYS0_LCS	0x3
+#endif
 
 /* Data */
-#define TTYS0_RBR (TTYS0+0x00)
+#define TTYS0_RBR (TTYS0_BASE+0x00)
 
 /* Control */
 #define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (TTYS0+0x01)
-#define TTYS0_IIR (TTYS0+0x02)
+#define TTYS0_IER (TTYS0_BASE+0x01)
+#define TTYS0_IIR (TTYS0_BASE+0x02)
 #define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (TTYS0+0x03)
-#define TTYS0_MCR (TTYS0+0x04)
+#define TTYS0_LCR (TTYS0_BASE+0x03)
+#define TTYS0_MCR (TTYS0_BASE+0x04)
 #define TTYS0_DLL TTYS0_RBR
 #define TTYS0_DLM TTYS0_IER
 
 /* Status */
-#define TTYS0_LSR (TTYS0+0x05)
-#define TTYS0_MSR (TTYS0+0x06)
-#define TTYS0_SCR (TTYS0+0x07)
+#define TTYS0_LSR (TTYS0_BASE+0x05)
+#define TTYS0_MSR (TTYS0_BASE+0x06)
+#define TTYS0_SCR (TTYS0_BASE+0x07)
 
 	jmp	serial0
 
@@ -300,19 +321,21 @@ serial0:
 	/* Set 115.2Kbps,8n1 */
 	/* Set 8bit, 1 stop bit, no parity, DLAB */
 	mov	$TTYS0_LCR, %dx
-	mov	$0x83, %al
+	mov	$(TTYS0_LCS | 0x80), %al
 	out	%al, %dx
 
 	/* set Baud Rate Divisor to 1 ==> 115200 Buad */
 	mov	$TTYS0_DLL, %dx
-	mov	$0x01, %al
+	mov	$TTYS0_DIV_LO, %al
 	out	%al, %dx
 	mov	$TTYS0_DLM, %dx
-	mov	$0x00, %al
+	mov	$TTYS0_DIV_HI, %al
 	out	%al, %dx
 
 	/* Disable DLAB */
 	mov	$TTYS0_LCR, %dx
-	mov	$0x03, %al
+	mov	$(TTYS0_LCS & 0x7f), %al
 	out	%al, %dx
 
+	TTYS0_TX_STRING($ttyS0_test)
+

src/ram/ramtest.inc

@@ -1,4 +1,3 @@
-
 	/*
 	 * This is much more of a "Is my SDRAM properly configured?"
 	 * test than a "Is my SDRAM faulty?" test.  Not all bits
@@ -6,6 +5,7 @@
 	 */
 	
 	jmp	rt_skip
+	.section ".rodata"
 
 rt_test:	.string "Testing SDRAM : "
 rt_fill:	.string "SDRAM fill:\r\n"
@@ -13,6 +13,7 @@ rt_verify:	.string "SDRAM verify:\r\n"
 rt_toomany:	.string "Too many errors.\r\n"
 rt_done:	.string "Done.\r\n"
 	
+	.text
 ramtest:
 #ifdef RAMTEST
 	mov %eax, %esi

src/southbridge/intel/82801/82801.h

@@ -0,0 +1,2 @@
+#define SERIRQ_CNTL	0x64
+#define GEN_CNTL	0xd0

src/southbridge/intel/82801/Config

@@ -0,0 +1,3 @@
+object nvram.o
+object ich2_ioapic.o
+object ich2_lpc.o

src/southbridge/intel/82801/ich2_ioapic.c

@@ -0,0 +1,15 @@
+#include <pci.h>
+#include <pci_ids.h>
+#include "82801.h"
+void ich2_enable_ioapic(void)
+{
+	struct pci_dev *dev;
+	u32 dword;
+	dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F0, 0);
+	if (!dev) {
+		return;
+	}
+	pci_read_config_dword(dev, GEN_CNTL, &dword);
+	dword |= (3 << 7);
+	pci_write_config_dword(dev, GEN_CNTL, dword);
+}

src/southbridge/intel/82801/ich2_lpc.c

@@ -0,0 +1,13 @@
+#include <pci.h>
+#include <pci_ids.h>
+#include "82801.h"
+void ich2_enable_serial_irqs(void)
+{
+	struct pci_dev *dev;
+	u32 dword;
+	dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F0, 0);
+	if (!dev) {
+		return;
+	}
+	pci_write_config_byte(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
+}

src/southbridge/intel/82801/nvram.c

@@ -0,0 +1,8 @@
+#include <part/nvram.h>
+#include <printk.h>
+
+void nvram_on(void)
+{
+	printk_notice("Please turn on nvram\n");
+	return;
+}

src/superio/winbond/w83627hf/setup_serial.inc

@@ -8,41 +8,50 @@
 #define SIO_INDEX SIO_BASE
 #define SIO_DATA  SIO_BASE+1
 
+#define SIO_SYSTEM_CLK_INPUT_48MHZ	(1<<6)
+#define SIO_SYSTEM_CLK_INPUT_24MHZ	(0<<6)
+
+#if defined(SIO_SYSTEM_CLK_INPUT)
+#if (SIO_SYSTEM_CLK_INPUT != SIO_SYSTEM_CLK_INPUT_48MHZ) &&  (SIO_SYSTEM_CLK_INPUT != SIO_SYSTEM_CLK_INPUT_24MHZ) 
+#error BAD SIO_SYSTEM_CLK_INPUT_PARAMETER
+#endif
+#endif
+
+
 #define SIO_COM1_DEVICE 2
 
 #define SIO_ENTER_PNP_MODE() \
-	movw	$SIO_BASE, %dx	; \
-	movb	$0x87, %al	; \
-	outb	%al, %dx	; \
-	outb	%al, %dx
+	movb	$0x87, %al		; \
+	outb	%al, $(SIO_BASE)	; \
+	outb	%al, $(SIO_BASE)
 
 
 #define SIO_EXIT_PNP_MODE() \
-	movw	$SIO_BASE, %dx	; \
-	movb	$0xaa, %al	; \
-	outb	%al, %dx
+	movb	$0xaa, %al		; \
+	outb	%al, $(SIO_BASE)
 
 #define SIO_WRITE_CONFIG(value, reg) \
-	movw	$SIO_BASE, %dx	; \
-	movb	$reg, %al	; \
-	outb	%al, %dx	; \
-	incw	%dx		; \
-	movb	$value, %al	; \
-	outb	%al, %dx
+	movb	$reg, %al		; \
+	outb	%al, $(SIO_INDEX)	; \
+	movb	$value, %al		; \
+	outb	%al, $(SIO_DATA)
 
 #define SIO_READ_CONFIG(value, reg) \
-	movw	$SIO_BASE, %dx	; \
-	movb	$reg, %al	; \
-	outb	%al, %dx	; \
-	incw	%dx		; \
-	inb	%al, %dx
+	movb	$reg, %al		; \
+	outb	%al, $(SIO_INDEX)	; \
+	inb	%al, $(SIO_DATA)
 
 #define SIO_SET_LOGICAL_DEVICE(device) \
 	SIO_WRITE_CONFIG(device, 0x07)
 
-
-	/* enable serial 1 */
+	/* Enable pnp */
 	SIO_ENTER_PNP_MODE()
+
+#if defined(SIO_SYSTEM_CLK_INPUT)
+	/* Setup up the clock input */
+	SIO_WRITE_CONFIG(0x84 | SIO_SYSTEM_CLK_INPUT), 0x24)
+#endif
+	/* enable serial 1 */
 	SIO_SET_LOGICAL_DEVICE(SIO_COM1_DEVICE)
 	SIO_WRITE_CONFIG(1, 0x30)
 	SIO_WRITE_CONFIG(0x3, 0x60)

src/superio/winbond/w83627hf/superio.c

@@ -249,8 +249,6 @@ static void enable_devices(struct superio *sio)
 	setup_acpi_registers(sio);
 #endif
 
-	// what's this.
-	write_config(sio, 1, 0x30);
 	exit_pnp(sio);
 }
 

util/config/NLBConfig.py

@@ -42,7 +42,7 @@ def add_main_rule_dependency(new_dependency):
 # and an optional rule (can be empty) for actually building
 # the object
 def addobject(object, sourcepath, rule, condition):
-	objectrules.append([object, sourcepath, rule, condition])
+	objectrules.append([object, topify(sourcepath), rule, condition])
 
 # OK, let's face it, make sucks. 
 # if you have a rule like this: 
@@ -98,12 +98,11 @@ def common_command_action(dir, type, name):
 	return fullpath
 
 def set_arch(dir, my_arch):
-	global arch, makebase, crt0base, ldscriptbase
+	global arch, makebase, crt0base
 	arch = my_arch
 	configpath = os.path.join(treetop, os.path.join("src/arch/", os.path.join(my_arch, "config")))
 	makebase = os.path.join(configpath, "make.base")
 	crt0base = os.path.join(configpath, "crt0.base")
-	ldscriptbase = os.path.join(configpath, "ldscript.base")
 	print "Now Process the ", my_arch, " base files"
 	if (debug):
 		print "Makebase is :", makebase, ":"
@@ -510,22 +509,6 @@ def writecrt0(path):
 
 	file.close();
 
-# write ldoptions
-def writeldoptions(path):
-	ldfilepath = os.path.join(path, "ldoptions")
-	print "Trying to create ", ldfilepath
-#	try: 
-	file = open(ldfilepath, 'w+')
-
-	keys = makeoptions.keys()
-	keys.sort()
-	for key in keys:
-		value = makeoptions[key]
-		regexp = re.compile(r"^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$")
-		if value and regexp.match(value):
-			file.write("%s = %s;\n" % (key, value))
-		
-	file.close();
 
 # write doxygen file
 def writedoxygenfile(path):
@@ -554,38 +537,56 @@ def writedoxygenfile(path):
 
 
 
+def topify(path):
+	global treetop
+	if path[0:len(treetop)] == treetop:
+		path = path[len(treetop):len(path)]
+		if (path[0:1] == "/"):
+			path = path[1:len(path)]
+		path = "$(TOP)/" + path
+	return path
+
+
+def writemakefilesettings(path):
+	# Write Makefile.settings to seperate the settings
+	# from the actual makefile creation
+	# In practice you need to rerun NLBConfig.py to change
+	# these but in theory you shouldn't need to.
+	filename = os.path.join(path, "Makefile.settings")
+
+	print "Trying to create ", filename
+	keys = makeoptions.keys()
+	keys.sort()
+#	try: 
+	file = open(filename, 'w+')
+	file.write("TOP=%s\n" % (treetop))
+	for key in keys:
+		file.write("export %s:=%s\n" % (key, makeoptions[key]))
+	file.write("export VARIABLES := ");
+	for key in keys:
+		file.write("%s " % key)
+	for key in makenooptions.keys(): 
+		file.write("%s " % (key))
+	file.write("\n");
+
+
 # write the makefile
 # we're not sure whether to write crt0.S yet. We'll see. 
 # let's try the Makefile
 # first, dump all the -D stuff
 
 def writemakefile(path):
+	writemakefilesettings(path)
 	makefilepath = os.path.join(path, "Makefile")
 	mainboardinitfiles = command_vals['mainboardinit']
 	config_file_list = command_vals['config_files']
 	ldscripts = command_vals['ldscripts']
 
 	print "Trying to create ", makefilepath
-	keys = makeoptions.keys()
-	keys.sort()
-#	try: 
 	file = open(makefilepath, 'w+')
-	file.write("TOP=%s\n" % (treetop))
-	for key in keys:
-		if makeoptions[key] :
-			file.write("%s=%s\n" % (key, makeoptions[key]))
 
-	file.write("CPUFLAGS :=\n")
-	for key in keys: 
-#		print "key is %s, val %s\n" % (key, makeoptions[key])
-#		file.write("CPUFLAGS += %s\n" % (makeoptions[key]))
-		if makeoptions[key] :
-			file.write("CPUFLAGS += -D%s=\'%s'\n" % (key, makeoptions[key]))
-		else:
-			file.write("CPUFLAGS += -D%s\n" % (key))
-
-	for key in makenooptions.keys(): 
-		file.write("CPUFLAGS += -U%s\n" % (key))
+	file.write("include Makefile.settings\n")
+	file.write("include cpuflags\n")
 				
 	# print out all the object dependencies
 	# There is ALWAYS a crt0.o
@@ -599,9 +600,9 @@ def writemakefile(path):
 			file.write("OBJECTS-$(%s) += %s\n" % (obj_cond, obj_name))
 
 	# print out all ldscript.ld dependencies
-	file.write("LDSUBSCRIPTS-1 := %s\n" % ldscriptbase )
+	file.write("LDSUBSCRIPTS-1 := \n" )
 	for i in range(len(ldscripts)):
-		script = ldscripts[i][0];
+		script = topify(ldscripts[i][0]);
 		condition = ldscripts[i][1];
 		if condition:
 			file.write("LDSUBSCRIPTS-$(%s) += %s\n" % (condition, script))
@@ -648,10 +649,10 @@ def writemakefile(path):
 
 
 	# print out the dependencies for Makefile
-	file.write("Makefile crt0.S ldoptions nsuperio.c: %s $(TOP)/util/config/NLBConfig.py $(TOP)/src/arch/$(ARCH)/config/make.base $(TOP)/src/arch/$(ARCH)/config/crt0.base \n\tpython $(TOP)/util/config/NLBConfig.py %s $(TOP)\n" 
+	file.write("Makefile Makefile.settings crt0.S nsuperio.c: %s $(TOP)/util/config/NLBConfig.py $(TOP)/src/arch/$(ARCH)/config/make.base $(TOP)/src/arch/$(ARCH)/config/crt0.base \n\tpython $(TOP)/util/config/NLBConfig.py %s $(TOP)\n" 
 		% (config_file, config_file))
 	for i in range(len(config_file_list)):
-		file.write("Makefile: %s\n" % config_file_list[i])
+		file.write("Makefile: %s\n" % topify(config_file_list[i]))
 
 	file.close();
 #	except IOError:
@@ -685,7 +686,6 @@ treetop = command_vals['TOP']
 # set the default locations for config files
 makebase = os.path.join(treetop, "util/config/make.base")
 crt0base = os.path.join(treetop, "arch/i386/config/crt0.base")
-ldscriptbase = os.path.join(treetop, "arch/alpha/config/ldscript.base")
 doxyscriptbase = os.path.join(treetop, "src/config/doxyscript.base")
 
 ## now read in the base files. 
@@ -702,7 +702,6 @@ doconfigfile(treetop, config_file)
 #	print key, val
 
 writemakefile(outputdir)
-writeldoptions(outputdir)
 writecrt0(outputdir)
 writesuperiofile(outputdir)
 writedoxygenfile(outputdir)