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Typo in the HOWTO for SiS 630

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Quick patch for fix in the raminit code for 440gx == we need to fix this
monday.
This commit is contained in:
Ronald G. Minnich 2001-09-24 03:48:19 +00:00
parent cffb97e763
commit 2dfc41206b
3 changed files with 71 additions and 2 deletions
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2
HOWTO/SiS630
View file

@ -163,7 +163,7 @@ o You now need to figure out where you want to put your build images.
commandline root=/dev/hda1
# We're using disk on chip. Tell it where to find the docipl code
docipl northsouthbridge/sis/630
docipl northsouthbridge/sis/630/ipl.S
# Tell Config that we're going to use DOC Millenium as the source
# of the compressed image
option USE_DOC_MIL

29
src/northbridge/intel/440gx/northbridge.c
View file

@ -1,6 +1,34 @@
#include <pci.h>
#include <cpu/p5/io.h>
#include <printk.h>
void
dumpramregs(struct pci_dev *pcidev)
{
int i, j;
for(i = 0x50; i < 0x90; i += 16) {
printk_err("%02x: ", i);
for(j = 0; j < 16; j++) {
unsigned char val;
pci_read_config_byte(pcidev, i+j, &val);
printk_err("%02x ", val);
}
printk_err("\n");
}
for(i = 0xc0; i < 0xe0; i += 16) {
printk_err("%02x: ", i);
for(j = 0; j < 16; j++) {
unsigned char val;
pci_read_config_byte(pcidev, i+j, &val);
printk_err("%02x ", val);
}
printk_err("\n");
}
}
unsigned long sizeram()
{
/*
@ -23,6 +51,7 @@ unsigned long sizeram()
if (banks == 0) {
totalmem = 0x80000000UL;
}
dumpramregs(pcidev);
return totalmem;
}

42
src/northbridge/intel/440gx/raminit.inc
View file

@ -427,6 +427,12 @@ jmp intel_440_out
CS_WRITE_BYTE(0xee, 0x00) ; \
CS_WRITE_BYTE(0xef, 0x00)
/* PMCR -- BIOS sets 0x90 into it.
* 0x10 is REQUIRED.
* we have never used it. So why did this ever work?
*/
#define SET_PMCR \
CS_WRITE_BYTE(0x7a, 0x90);
ram_set_registers:
SET_NBXCFG
@ -443,6 +449,7 @@ ram_set_registers:
SET_MBFS
SET_DWTC
SET_DRTC
SET_PMCR
RET_LABEL(ram_set_registers)
@ -727,8 +734,30 @@ spd_set_dramc:
spd_set_dramc_out:
testb $0x12, %al
/* $8 is bit value for non-registered DRAM */
movl $8, %eax
jz 1f
/* this is a registered part.
* observation: for register parts, BIOS zeros (!)
* registers CA-CC. This has an undocumented meaning.
*/
xorl %edx, %edx
movl $0xca, %eax
PCI_WRITE_CONFIG_BYTE
xorl %edx, %edx
movl $0xcb, %eax
PCI_WRITE_CONFIG_BYTE
xorl %edx, %edx
movl $0xcc, %eax
PCI_WRITE_CONFIG_BYTE
/* next block is for Ron's attempt to get registered to work. */
#ifdef INTEL_RAM_TEST_REGISTERED
/* BIOS makes weird page size for registered! */
movl $2, %edx
movl $0x74, %eax
PCI_WRITE_CONFIG_BYTE
#endif
/* now set the bit value for registered sdram into %eax */
movl $0x10, %eax
1: movl %eax, %edx
movl $0x57, %eax
@ -949,7 +978,7 @@ spd_set_nbxcfg:
* we will do this in two steps, first or in 0x80 to 0x50.b,
* then or in 0x1 to 0x51.b
*/
mov %esi, %eax
mov %esi, %eax
cmpb $0xff, %al
je 1f
movl $0x50, %eax
@ -964,6 +993,17 @@ spd_set_nbxcfg:
movb %al, %dl
movl $0x51, %eax
PCI_WRITE_CONFIG_BYTE
// try this.
// we should be setting bit 2 in register 76 and we're not
// technically we should see if CL=2 for the ram,
// but registered is so screwed up that it's kind of a lost
// cause.
movl $0x76, %eax
PCI_READ_CONFIG_BYTE
orb $0x4, %al
movb %al, %dl
movl $0x76, %eax
PCI_WRITE_CONFIG_BYTE
1:
RET_LABEL(spd_set_nbxcfg)