Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.
Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().
Tested with a multiboot enhanced version of FILO.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4c1d95a8f4aa8735538dad85d5f856ce36a5f72e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 898de6111a
Original-Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18350
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/445141
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: I9043f9f0b66b45d04e8b8cbe8c99b77686fd5666
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4979d7610e
Original-Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: M Naveen <naveen.m@intel.com>
Original-Signed-off-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18211
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445127
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1c0e5acebce9db7e06e2e320dbdf67d6c63061b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0700dca969
Original-Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18312
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445124
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: I6d837f50db404f35606f1f975b05456946605c10
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2b194d9741
Original-Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18366
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444818
Implement the argc/argv passing as described in coreboots payload API:
http://www.coreboot.org/Payload_API
While at it, give the code some love by not needlessly trashing register
values.
BUG=none
BRANCH=none
TEST=none
Change-Id: If49874b1ac1c7359816f4ec02c5380c32101fa1a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: d2f16cac74
Original-Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18336
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444817
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.
Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.
Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.
BUG=none
BRANCH=none
TEST=none
Change-Id: I231828bb9a65a6b1077b17024c0c59fed8546284
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 57dc93c967
Original-Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18335
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444816
According to coreboots payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.
[1] https://www.coreboot.org/Payload_API
BUG=none
BRANCH=none
TEST=none
Change-Id: I1782c45b615d431de8be5a533d5890ed53ddb9d8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7b681c5926
Original-Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18334
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444815
According to coreboots payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.
[1] https://www.coreboot.org/Payload_API
BUG=none
BRANCH=none
TEST=none
Change-Id: I2acc66d20fcc4e313d1ddbc4a7bc1772548981c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 9fa78c136d
Original-Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444814
scan_smbus routine does not perform any smbus specific operation. Thus,
rename the routine to scan_generic_bus so that it can be used by other
buses like SPI. Add a wrapper scan_smbus to allow other users of smbus
scan to continue working as before.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Id2b6342d96915e47c265c7984f651680632a3903
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 4e08479688
Original-Change-Id: I8ca1a2b7f2906d186ec39e9223ce18b8a1f27196
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18363
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/444809
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.
Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: Id5ef64e11a862f4075afa06a7eca25bfc84fc9aa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 7606c377f5
Original-Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18340
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/444808
Update sconfig lex and yacc files to add support for a new "SPI" device
type in the devicetree. SPI device takes only parameter i.e. chip select
number for the device on the SPI bus.
Re-generate the shipped files for sconfig using flex 2.6.0 and bison
3.0.4 (make CONFIG_SCONFIG_GENPARSER=1). Clean up local paths that leak
into generated files.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: If1595a4b6c5a3902f04dd0270a927c3dd418db48
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: e67002968b
Original-Change-Id: If0831e25b3e4ed87827ad92356d7bf47b6387884
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18339
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444807
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
BUG=none
BRANCH=none
TEST=none
Change-Id: I92d9ceec19d236e756c4eaf2ecf9c0534a3ad482
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 901efea8ab
Original-Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Original-Signed-off-by: Mathias Krause <minipli@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18332
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443927
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic79be51b2d99ebbc2629e19f6110ad10f12028ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 6abdbcd4dc
Original-Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18292
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/443925
The four options are only used in X86:
- BOOTBLOCK_SIMPLE
- BOOTBLOCK_NORMAL
- BOOTBLOCK_SOURCE
- SKIP_MAX_REBOOT_CNT_CLEAR
Move them all into src/arch/x86/Kconfig - this puts them in the chipset
menu instead of general setup.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: If9a61ed8a0b9add3b4f70dfb15ea0213c452f584
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 408fda799a
Original-Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17909
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/443682
For boolean types, 'n' is the default default value - it doesn't
NEED to be set. If it IS set, it prevents a later default from
being set. So by removing the 'default n' statements from the
early symbols, they can be overridden other places in the tree.
Verified that this makes no significant changes to any config file.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1d6e0be8feb731f073b7b3815504e6cd1957976
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: c8d16f4933
Original-Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17908
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443681
Some variants need the internal pull resistor on GPIO_SSUS_40
set explicitly to pull down rather than disabling the pull,
in order for the ram-id to be read correctly via GPIO.
Correct this by adding a function to enable and set the internal pull
and define its use as needed in the board's variant.h.
Chromium source:
branch: firmware-gnawty-5216.239.B
/src/soc/intel/baytrail/baytrail/gpio.h#418
/src/mainboard/google/gnawty/romstage.c#60
Test: boot 4GB Candy board and observe correct RAM id, amount detected
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia648846f4cdf65908db9a310b201562f0ff72951
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 474a7c51ce
Original-Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18309
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/443676
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4aa3ebf50bc772ff0baf0b6c685022ea40750234
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: d81078d944
Original-Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18294
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/443675
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, CONFIG_NO_FADT_8042 was added to selectively
disable 8042 on FADT.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: I45e667950850209b33531dbb7ed784f073648e69
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 2864f85725
Original-Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443672
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.
On Kevin board, if we connect usb device with Samsung U2 cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.
This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.
BRANCH=gru
BUG=chrome-os-partner:62320
TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into
Type-C port, check if the USB device can be detected.
Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/431015
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The children of Gru should share the benefits. In the real world, Bob can't
pass the eye diagram tests.
BUG=chrome-os-partner:62714
BRANCH=firmware-gru-8785.B
TEST=build coreboot
Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/440745
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 0e47999829af8b78a30c4cece47455ffb1f9268e)
Reviewed-on: https://chromium-review.googlesource.com/441468
Void pointer arithmetics are forbidden in standard C but GCC has
an extension that allows it.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id10d81e0663007c10a9a139cc437dd94be654212
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 85cfddb4b4
Original-Change-Id: I43029b2ab2f7709b8e1ba85eb05c31341b8ac16f
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18293
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/441809
Performance degradation seen with current PL1 throttling rate as 8
seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1
throttling rate to 15 seconds, fps score improved.
BUG=chrome-os-partner:60038
BRANCH=reef
TEST=Built and tested on electro system
Change-Id: I9aed66ecb958bc32be5013ddc638dcbe42cd4e89
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d96669e9db
Original-Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18317
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/441808
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icccf8c3113c0491ffc31d1ff04177b2116df8b17
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e3c59e258
Original-Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18265
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441807
Since it checks for DDR3 style checksums, it's a more appropriate name.
Also make its configuration local for a future code move.
BUG=none
BRANCH=none
TEST=none
Change-Id: I863c33342228fa73b60c31fd86d493774de1a6fd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e08b59cdc
Original-Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18264
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/441806
Also make sure that no board changes behaviour because of that by adding
a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if
DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the
device/dram code).
Change-Id: Ia07abeec2b457f2e822fee3e9f09062208e54f33
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44a46a1f04
Original-Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18254
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/441804
Shorten field names of struct cbmem_console since saying "buffer_" in
front of everything is redundant and we can use the gained space to save
some line breaks in the code later. This also aligns the definition with
the version in libpayload.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib8fbc84ffcca85532558c6d7f98cb0a433a10c28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d09dc6b442
Original-Change-Id: I160ad1f39b719ac7e912d0466c82a58013cca0f9
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18299
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/440168
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I817c13aaac891f5aef075ba66d8d66aba2346f97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ff7e8f550
Original-Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18285
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440166
The apollolake boards don't have an me.bin proper, but they still have
descriptor regions which need to be locked down. Therefore, remove the
restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE.
BUG=chrome-os-partner:62177
TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE.
Change-Id: I420578dd0002135be172abfc4681ffd6d3d6f43d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0254c2d99f
Original-Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18304
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/440165
Dump the CSE status registers for potential debugging purposes.
Explicitly call out manufacturing mode of the part since it's
important shipping devices ensure manufacturing mode is locked
down. Intel is planning on writing a common driver so a complete
status -> string dumps was not done because (surprise surprise)
not all the fields are equal with previous implementations.
BUG=chrome-os-partner:62177
BRANCH=reef
TEST=Booted and noted dump of CSE status registers.
Change-Id: Ia3466f5551fbd907350c9d9f358c79a08da39fac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d14af8154
Original-Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18303
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/440164
This fixes an issue on systems where the S3 state in the pm1 control
registers are not cleared when vboot determines recovery mode is
required on an S3 resume. The EC code will reboot the system knowing
that the EC was in RW. However, on subsequent entry into romstage the
S3 path will be taken and fails to recover cbmem -- forcing another
reboot. To work around that, signal to the platform a reboot is
happening and let the platform perform the necessary fix ups to the
register state.
BUG=chrome-os-partner:62627
Change-Id: I2c0bdffb80979954021203c798cf9bce56eca7d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96a4317fa9
Original-Change-Id: Ic144b11b4968c92a1273b8d9eb9dc10f0056bf3d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18295
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439150
