Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: mainboard/google/reef: Increase PL1 sampling period

Browse source 
Performance degradation seen with current PL1 throttling rate as 8
seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1
throttling rate to 15 seconds, fps score improved.

BUG=chrome-os-partner:60038
BRANCH=reef
TEST=Built and tested on electro system

Change-Id: I9aed66ecb958bc32be5013ddc638dcbe42cd4e89
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d96669e9db
Original-Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18317
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/441808
This commit is contained in:
Sumeet Pawnikar 2017-02-10 11:13:36 +05:30 • committed by chrome-bot
parent 1a5c5c165b
commit cc9cbb7cf9
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
View file

@ -61,7 +61,7 @@ Name (DTRT, Package () {
#endif
/* CPU Effect on Temp Sensor 1 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },