Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8865b57dafe5df73e82255367562698b1a0a56b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: deed5fbebd
Original-Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18109
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428264
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S,
so that it is associated with FSP driver version that is being used.
Tested on Kabylake Rvp11.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32a6ede3d310f9a48fce42f47d4eeb729abb53da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 15b7163821
Original-Change-Id: I869df6eb746e3982e5912c272255eab6cb008838
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18083
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428261
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD entry "wifi_sar" is required to supply the raw SAR
limit data.
BUG=chrome-os-partner:60821
TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot,
check the SSDT dump and verify WRDS and EWRD structures.
Change-Id: I3dc4219676f1b4cfb108d15ec25f4c992e0367e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3dea69a487
Original-Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17959
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428260
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5aadea9d76
Original-BUG=chrome-os-partner:61803
Original-BRANCH=reef
Original-TEST=emerge-pyro coreboot
Original-Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I63d4092acbb26602df9c501b8d87bfb3169ee79d
Reviewed-on: https://chromium-review.googlesource.com/428259
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This updates the configuration for ARM CrOS devices (nyans and veyrons)
by using the CHROMEOS Kconfig option, thus reducing the number of
options to select. It also brings proper serial console support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I455b66801c3518319e078aa63d63b515ee80cd22
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a9ec36fd4
Original-Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/17928
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428258
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
mvmap2315_reset() is called from locations where we're checking for NULL
pointers. Because coverity can't tell from the code that the functions
are not returning, it's showing errors of accessing pointers after
we've determined that they're invalid.
Mark it as noreturn, and add a loop in case the reset isn't on the
next instruction. This probably isn't needed, but shouldn't hurt.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icabde50124ed8206a0a114cd10002ef81a770f57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3051cd9265
Original-Found-by: Coverity Scan #1362809
Original-Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18103
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428257
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Other chips dump tco_status here if it wasn't handled, which makes
sense.
tco_sts can't be zero here, because the call would have already returned
if it were. Also, dump_tco_status wouldn't print anything if tco_sts
were zero.
This will still only print the debug information if DEBUG_SMI is
enabled in Kconfig, so in general, this change won't have much of an
effect on anything.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icfe18802dfe054409e3e0ca111a3a0c272ab2a2d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e3b858888
Original-Found-by: Coverity Scan #1229598
Original-Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18101
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428256
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
This should always have been an and, not an or.
The only way this would happen is if no GPIOs were getting configured,
so we shouldn't ever have a NULL here, but if we did, GPIOs would
be randomly configured, which would have 'interesting' results.
BUG=none
BRANCH=none
TEST=none
Change-Id: I480ac3acde34c2f3d44424a001065f37a2428d72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e4cb50420
Original-Found-by: Coverity Scan #1229633 & 1229632
Original-Change-Id: If123372658383f84279738e1186425beba3208ca
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18095
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428255
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
On Chrome OS devices that use TPM2 parts the platform hierarchy
is disabled by the boot loader, depthcharge. Since the bootloader
isn't involved in resuming a suspended machine there's no equivalent
action in coreboot to disable the platform hierarchy. Therefore, to
ensure consistent state in resume the platform hierarchy in the TPM2
needs to be disabled as well. For systems that resume using the
firmware the platform hierarchy is disabled when utilizing
TPM2 devices.
BUG=chrome-os-partner:61097
BRANCH=reef
TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start
trunksd' shows that phEnable is 0.
Change-Id: I144a36d8ff10ce92d3de0b26d924fd85468a9764
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f56c7787ba
Original-Change-Id: I060252f338c8fd68389273224ee58caa99881de8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18096
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428254
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The orphaned Tab_TrefT_k causes a failure to build due to
an unused variable warning on GCC 6. Remove this variable.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib66ec10a6babbc59814ed51d244af2ef75306b96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 17b66c3846
Original-Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18094
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/428253
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4a743faf8fdcc7b26c9fe2ed43ce10a539f79e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fb64d0b88
Original-Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Original-Found-by: Coverity Scan #1291162
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/428252
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Build issues were somehow overlooked in commit
ed840023a8:
1. hexstrtobin is not defined (needs the lib.h);
2. coreboot default compiler doesn't like variable initialization
within for loop.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: Iaf8ccf86e3b53fac481f28356d838728149d3e49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id:
Original-Change-Id: I85b1394956ceb9b64e1b72f9f71982b6205d5a99
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Original-Commit-Id: feb4ef6d92
Original-Original-Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0
Original-Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Original-Reviewed-on: https://review.coreboot.org/18076
Original-Original-Tested-by: build bot (Jenkins)
Original-Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428251
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions. Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0a31097c60af1fa050b6794ed5d631a7aa4c0d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 590a3e1f6c
Original-Found-by: Coverity Scan #1347337
Original-Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18079
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428249
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The FSP 2.0 change broke the logic for determining whether or not
to execute the GOP binary. Modify the FSP 2.0 code to do the right
thing and check for display_init_required() before passing VBT into
FSP and the GOP binary.
BUG=chrome-os-partner:61726
TEST=disable developer mode and ensure FSP does not run GOP
Change-Id: I9c607739eb791bbb4351059d2528c194328f6b95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d48410631
Original-Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18084
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/428248
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing DRAM clock speed to configuration value logic contained
an error resulting in a theoretical out of bounds read. While this
would not be hit on real hardware, it was prudent to clean up the
logic to avoid the associated Coverity warning.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57792539445f2026f5c88445ebce1e0ae026c60a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f9468f019
Original-Found-by: Coverity Scan #1347353
Original-Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18073
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/428245
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended. Fix the calls to the maximum read latency
training function.
BUG=none
BRANCH=none
TEST=none
Change-Id: I020e2cf73a59d31d83ce63392f39419e714f0fd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fa624784e
Original-Found-by: Coverity Scan #1347354
Original-Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18072
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428244
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Fix SPI flash ops regressions after commit:
c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING
When spi_flash_cmd() is called with argument response==NULL,
only send out command without reading back the response.
BUG=none
BRANCH=none
TEST=none
Change-Id: I618a26349ff21649cc908562d19d8e367f2e24bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 85b2b27e33
Original-Change-Id: I28a94f208b4a1983d45d69d46db41391e267891d
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18082
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/428242
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The critical delay delta was incorrectly specified as an
unsigned short. Use a signed short instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id41a1e68498d987db502f082a9402e34f5aa0c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5153cbfeb3
Original-Found-by: Coverity Scan #1347355
Original-Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18071
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428241
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing logic to set up CsMux45 used an incorrect mask
and comparison value due to a copy + paste editing error.
Use the correct mask and comparison value for the last two
values.
BUG=none
BRANCH=none
TEST=none
Change-Id: I07b094e8d748ee30d6147f6e183522705a0a8b4f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf1cb5b2d4
Original-Found-by: Coverity Scan #1347385
Original-Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18070
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/428240
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing code waiting for northbridge P-state transitions
contained a logical error preventing correct operation. Fix
the logical error and force coreboot to wait for the P-state
transitions per the BKDG.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibc395db02f423594f4c1c0bd219538f9318fb819
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aeaabd3fa3
Original-Found-by: Coverity Scan #1347388
Original-Change-Id: I35f498c836db1439734abe684354c18c8e160368
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18069
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428239
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The code to set the igd frequencies is written with the mobile version
of the 945 chipset in mind and seems to cause cause strange igd
related problems on the desktop versions.
Some possible problems are:
* on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
* on 800MHz fsb CPU memtest results vary a lot;
* since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
variant board scheme" that does not affect this northbridge, the
display shows garbage as soon as Linux (4.8) modesets the display.
A fix is to hardcode the core display and render clocks to their
maximum, potentially also improving graphical performance.
Vendor bios on all boards in coreboot with this northbridge have the
same value in this PCI config address.
TESTED on P5GC-MX (display works fine again in Linux) and
user reports of it making GA-945GCM-S2L run more stable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I47a2d4b2a12981d8c644108499230bc92769f1f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1853781748
Original-Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17981
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427477
On AMD DDR3 platforms, the upper DQMask was incorrectly
calculated, leading to undefined behaviour and possible
DRAM training faults. Use the correct calculation for
the upper DQMask.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibefa976ee627cf5d2515bf3aa52f65795dc6e303
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 21b01b80d6
Original-Found-by: Coverity Scan #1347394#1347393
Original-Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18068
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/427476
The Lenovo T400 has a CPU socket that can fit quad cores.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4a6d7ef1e07175b9f776c63e7323347a00ac2485
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccc042b821
Original-Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18059
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427475
Several members of DCTStatStruc are designed to persist across resets of
all other members. Move the persistent members into a substructure in
order to simplify the reset logic and avoid compiler warnings / UB.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibaf1d4adf0eaba178a731d85acaf7b0192077209
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a4dcdca7ba
Original-Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18058
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427473
AMDFWTOOL calculates the location of the amdfw based on the
CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the
resulting rom does not boot.
This patch forces the position of HUDSON_FWM_POSITION to be the
position calculated by amdfwrom.
Tested on a Bettong derivative with a 16MiB flash.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7edd584f61087005db19c4ab331b8bce6e30309
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c42424ec1
Original-Change-Id: I3ce69f77174327c18ff97e551c0665c9f633991e
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17934
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/427472
AMDFWTOOL calculates the location of the amdfw based on the
CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the
resulting rom does not boot.
This patch forces the position of HUDSON_FWM_POSITION to be the
position calculated by amdfwrom.
Tested on a Bettong derivative with a 16MiB flash.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iddd79a218e41611adda77c5e52366e8857d8b084
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: baae959a63
Original-Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17925
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/427471
There are systems that come with curl but not wget (eg macOS) and they
now have to install one less additional dependency.
Also fix some cosmetic issues in console output and require valid
certificates on https downloads.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1005b5f46fd2d79cf7f506c1e83280ff50fafa78
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: df1ff231e4
Original-Change-Id: Idc2ce892fbb6629aebfe1ae2a95dcef4d5d93aca
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18048
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427470
Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2477affed9f5d910ce657a809962356193eeb85f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0288d676
Original-Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17918
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/427469
When running abuild outside of jenkins, because all of the builds are
printed intermixed, it's easy to miss when a board has failed the build
by looking at the output. This saves a list of failed builds and prints
the list at the end of the run.
- Add a command line option to mark when abuild is being called
recursively.
- Add all failed builds to a list.
- Print the list when a non-recursive abuild run exits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9d84e4d85427ad39d9ed6607b9665ba8ed37f667
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 047c2f44b0
Original-Change-Id: Icb40ed8083a57bbcde49297d2b0814f98dcbb6c8
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17890
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427467
Variable name of inteltoolArgs was fixed.
The way of passing arguments to inteltool was changed from "-a -f"
to "-af" which is better as the string seems to be parsed
as a single argument.
BUG=none
BRANCH=none
TEST=none
Change-Id: I48729ca606b86f2a73b9c1dd2be686ba482906cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6bd18f6b5
Original-Change-Id: I0c48fb1e912261748ba9e2b91c291bac28b9e856
Original-Signed-off-by: Sebastian 'Swift Geek' Grzywna <swiftgeek@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18050
Original-Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427466
A VPD entry "wifi_sar" needs to be created which contains a heximal
encoded string in length of 40 bytes. get_wifi_sar_limits() function
retrieves and decodes the data from the VPD entry, which would later
be consumed by platform code.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: I73333bef1fec2769f4edb52c3e1f7262070ec5df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed840023a8
Original-Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17958
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427465
Gerrit will let you push a patch without a signed-off-by line,
although I believe it can't actually be merged. Instead of catching
it either manually, or when the patch is attempting to be merged,
catch this in the jenkins builder.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5964d9b029ddbc72e39ca9c9db0def8d9f8d61b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23ceb7d240
Original-Change-Id: I80161befa157266dd4e3209839a06ff398aab6bb
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17941
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/427464
Some PCI peripherals, such as FPGA accelerators, require a great amount
of memory mapped IO. This patch allows the user to select at build time
the bottom IO to leave enough space for such devices.
We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated.
BUG=none
BRANCH=none
TEST=none
Change-Id: If3289ef28c08a2e18b0095ff2be3091e40f1acfa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a132892de6
Original-Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d
Original-Credit-to: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17980
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/427463
Because Kconfig default values *ONLY* get set when they are first
configured, if you switch mainboards with an existing .config,
the values will not be set as expected for the new board.
This seems to confuse most users, so put a warning in a visible
location to let them know.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib4e35cf71c5777adbd15132ad8c7414aadfe4d27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3e26796c4
Original-Change-Id: Ie6a9c2d139ecd841d654943f14c119ebafd632f2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17939
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/427462
After we set the GET_TIME bit, the rtc time can't be read immediately. We
should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading
RTC time will return a old time.
BUG=chrome-os-partner:61078
BRANCH=veyron
TEST=Build and Boot
Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/423272
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/427522
Reviewed-by: Julius Werner <jwerner@chromium.org>
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
compatibility") bypass ODT to set the max driver strength for
the Type-C otg-port, it works well on otg-port when connected
with USB2.0 devices.
Unfortunately, because the Type-C otg-port and host-port are
consisted in one USB2 PHY, so bypass ODT will have an effect
on both host-port and otg-port. I have tested the host-port
eye-diagram, the result shows that if we bypass ODT, the host-
port eye-diagram height will become to high, more than 500mv,
this may cause USB 2.0 high-speed enumeration failure.
This patch bypass ODT for host-port separately, and then we
can reduce the host-port driver strength without affecting
the otg-port driver strength.
BRANCH=gru
BUG=chrome-os-partner:60727
TEST=Boot system, run 'lsusb' command and check if the usb camera
and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
on usb 1.1 hub, the issue happens. If not, try to run camera app
and then close camera app, repeat until find that the usb camera
is on the usb 1.1 hub.
Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/425739
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.
Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.
BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.
Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/426338
Reviewed-by: Douglas Anderson <dianders@chromium.org>
BUG=chrome-os-partner:56947
TEST=Verifed country code can be parsed from VPD in depthcharge.
BRANCH=None
Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc
Signed-off-by: Kan Yan <kyan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/425819
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.
Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18047
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425987
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
