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UPSTREAM: skylake: Do not pass VBT to FSP if display init not required

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The FSP 2.0 change broke the logic for determining whether or not
to execute the GOP binary.  Modify the FSP 2.0 code to do the right
thing and check for display_init_required() before passing VBT into
FSP and the GOP binary.

BUG=chrome-os-partner:61726
TEST=disable developer mode and ensure FSP does not run GOP

Change-Id: I9c607739eb791bbb4351059d2528c194328f6b95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d48410631
Original-Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18084
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/428248
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2017-01-09 22:23:39 -08:00 • committed by chrome-bot
parent cc129acf7f
commit 15f8ac0716
1 changed files with 12 additions and 2 deletions
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14
src/soc/intel/skylake/chip_fsp20.c
View file

@ -14,6 +14,7 @@
*/
#include <chip.h>
#include <bootmode.h>
#include <bootstate.h>
#include <device/pci.h>
#include <fsp/api.h>
@ -108,9 +109,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
/* Load VBT */
if (!is_s3_wakeup)
if (is_s3_wakeup) {
printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
} else if (display_init_required()) {
/* Get VBT data */
vbt_data = fsp_load_vbt();
if (vbt_data)
printk(BIOS_DEBUG, "Passing VBT to GOP\n");
else
printk(BIOS_DEBUG, "VBT not found!\n");
} else {
printk(BIOS_DEBUG, "Not passing VBT to GOP\n");
}
params->GraphicsConfigPtr = (u32) vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {