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UPSTREAM: amd/mct/ddr3: Wait for northbridge P-state transitions

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The existing code waiting for northbridge P-state transitions
contained a logical error preventing correct operation.  Fix
the logical error and force coreboot to wait for the P-state
transitions per the BKDG.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibc395db02f423594f4c1c0bd219538f9318fb819
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aeaabd3fa3
Original-Found-by: Coverity Scan #1347388
Original-Change-Id: I35f498c836db1439734abe684354c18c8e160368
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18069
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428239
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Timothy Pearson 2017-01-09 12:33:22 -06:00 • committed by chrome-bot
parent 83630efc37
commit 25a0d3573c
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -6737,7 +6737,7 @@ void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat,
/* Wait until CurNbPState == NbPstateLo */
do {
dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174);
} while (((dword2 << 19) & 0x7) != (dword & 0x3));
} while (((dword2 >> 19) & 0x7) != (dword & 0x3));
}
dword = Get_NB32(pDCTstat->dev_nbctl, 0x170);
dword &= ~(0x3 << 6); /* NbPstateHi = 0 */
@ -6748,7 +6748,7 @@ void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat,
/* Wait until CurNbPState == 0 */
do {
dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174);
} while (((dword2 << 19) & 0x7) != 0);
} while (((dword2 >> 19) & 0x7) != 0);
}
}
}