UPSTREAM: intel/i82801dx: Support 2MiB FWH part

Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2477affed9f5d910ce657a809962356193eeb85f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0288d676
Original-Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17918
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/427469

src/southbridge/intel/i82801dx/Kconfig

@@ -29,4 +29,8 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/intel/i82801dx/bootblock.c"
+
 endif

src/southbridge/intel/i82801dx/bootblock.c

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+static void bootblock_southbridge_init(void)
+{
+	/* Set FWH IDs for 2 MB flash part. */
+	if (CONFIG_ROM_SIZE == 0x200000)
+		pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
+}