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UPSTREAM: amd/mct/ddr3: Fix incorrect DQ mask calculation

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On AMD DDR3 platforms, the upper DQMask was incorrectly
calculated, leading to undefined behaviour and possible
DRAM training faults.  Use the correct calculation for
the upper DQMask.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibefa976ee627cf5d2515bf3aa52f65795dc6e303
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 21b01b80d6
Original-Found-by: Coverity Scan #1347394 #1347393
Original-Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18068
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/427476
This commit is contained in:
Timothy Pearson 2017-01-09 12:13:52 -06:00 • committed by chrome-bot
parent c86f471f0b
commit f79dac2631
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
View file

@ -1073,7 +1073,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x27c, dword);
} else if (lane < 8) {
Set_NB32_DCT(dev, dct, 0x274, ~0x0);
Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8)));
Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8)));
dword = Get_NB32_DCT(dev, dct, 0x27c);
dword |= 0xff; /* EccMask = 0xff */
Set_NB32_DCT(dev, dct, 0x27c, dword);
@ -1170,7 +1170,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x27c, dword);
} else if (lane < 8) {
Set_NB32_DCT(dev, dct, 0x274, ~0x0);
Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8)));
Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8)));
dword = Get_NB32_DCT(dev, dct, 0x27c);
dword |= 0xff; /* EccMask = 0xff */
Set_NB32_DCT(dev, dct, 0x27c, dword);