The new name and location make more sense:
- The instruction used to call into machine mode isn't called "ecall"
anymore; it's mcall now.
- Having SBI_ in the name is slightly wrong, too: these numbers are not
part of the Supervisor Binary Interface, they are just used to
forward SBI calls (they could be renumbered arbitrarily without
breaking an OS that's run under coreboot).
Also remove mcall_dev_{req,resp} and the corresponding mcall numbers,
which are no longer used.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71a96971f46d515a66d5f77497b40d891c1b5fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c5ebb1d005
Original-Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18146
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/430174
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
1. Disable WP
2. Pass SD card detect info in ACPI
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Verified that OS is able to detect SD card and read/write to it.
Change-Id: Id16f21dd70798b2e1c6e7af1d163e7089b66b46c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d093e4a387
Original-Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18138
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430172
poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: I80eab8bc6fb486bab959ab308c93d1d3031247bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4a159706e
Original-Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18133
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430171
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
SBI calls, as it turned out, were never right.
They did not set the stack correctly on traps.
They were not correctly setting the MIP instead of the SIP
(although this was not really well documented).
On Harvey, we were trying to avoid using them,
and due to a bug in SPIKE, our avoidance worked.
Once SPIKE was fixed, our avoidance broke.
This set of changes is tested and working with Harvey
which, for the first time, is making SBI calls.
It's not pretty and we're going to want to rework
trap_util.S in coming days.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1a4fa2ddec9b556ec2da574e080f9a77ef139203
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f3a53b6f6
Original-Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99
Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18097
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/430170
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
it may cause edp aux transfer error if set the edp pclk clock too high,
so reduce it to 25MHz.
BUG=chrome-os-partner:60130
BRANCH=None
TEST=Build and Boot
Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/429410
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
power button is usually dropped because it's not
in the keyboard matrix range. Adding in condition
to forward it like other keys.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot and make sure power button selection
in detachable menus is processed on reef.
Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428199
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This code allows people to override the usb2 eye pattern
UPD settings for boards.
BUG=chrome-os-partner:61031
BRANCH=None
TEST=Usb2 function ok and make sure fsp upd is overridden
Change-Id: I9e4cc098e5e51f178ab00f7b4d56c4ba099a279c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9d490daf8d
Original-Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18060
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427765
These updated header files contain USB tuning parameters as well as
some general cleanup of unused parameters in the UPD Headers. This
patch along with the upcoming FSP 1.3.0 release will allow for USB
tuning on apollolake platforms.
CQ-DEPEND=CL:*315403
BUG=chrome-os-partner:61031
Change-Id: Icfd57b5358e5598618d7a91af6ba74baddee2fc0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7056a82e0
Original-Change-Id: Id7cce1ea83057630d508523ada18c5425804535e
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18046
Original-Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
cbfstool ... add ... -c precompression assumes the input file to be
created by cbfs-compression-tool's compress command and uses that to add
the file with correct metadata.
When adding the locale_*.bin files to Chrome OS images, this provides a
nice speedup (since we can parallelize the precompression and avoid
compressing everything twice) while creating a bit-identical file.
BUG=chromium:630451
BRANCH=none
TEST=with the necessary tweaks to the build system,
emerge-kevin chromeos-bootimage takes 0:25 instead of 3:10 before on the
z620 I work on, about a magnitude faster.
Change-Id: Ib99b8c4960e174ea5b9a5077ca49992a93d7bd41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Change-Id: Iadd106672c505909528b55e2cd43c914b95b6c6d
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18102
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427703
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
cbfs-compression-tool provides a way to benchmark the compression
algorithms as used by cbfstool (and coreboot) and allows to
pre-compress data for later consumption by cbfstool (once it supports
the format).
For an impression, the benchmark's results on my machine:
measuring 'none'
compressing 10485760 bytes to 10485760 took 0 seconds
measuring 'LZMA'
compressing 10485760 bytes to 1736 took 2 seconds
measuring 'LZ4'
compressing 10485760 bytes to 41880 took 0 seconds
And a possible use for external compression, parallel and non-parallel
(60MB in 53 files compressed to 650KB on a machine with 40 threads):
$ time (ls -1 *.* |xargs -n 1 -P $(nproc) -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA)
real 0m0.786s
user 0m11.440s
sys 0m0.044s
$ time (ls -1 *.* |xargs -n 1 -P 1 -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA)
real 0m10.444s
user 0m10.280s
sys 0m0.064s
BUG=chromium:630451
BRANCH=none
TEST=manual execution of the tool works
Change-Id: If2ac452dae4180b5df516a99808008ce41922621
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Change-Id: I40be087e85d09a895b1ed277270350ab65a4d6d4
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18099
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/427702
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
This speeds up the lzma encoder approximately four-fold.
BUG=chromium:630451
BRANCH=none
TEST=emerge-$board chromeos-bootimage's set of adding static assets it
noticeably faster
Change-Id: Ie8cc9b6106ac72c0b0e96bcd76bb7d13d48b2025
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Change-Id: Ibf896098799693ddd0f8a6c74bda2e518ecea869
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18098
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/427701
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8865b57dafe5df73e82255367562698b1a0a56b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: deed5fbebd
Original-Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/18109
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428264
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S,
so that it is associated with FSP driver version that is being used.
Tested on Kabylake Rvp11.
BUG=none
BRANCH=none
TEST=none
Change-Id: I32a6ede3d310f9a48fce42f47d4eeb729abb53da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 15b7163821
Original-Change-Id: I869df6eb746e3982e5912c272255eab6cb008838
Original-Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18083
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428261
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD entry "wifi_sar" is required to supply the raw SAR
limit data.
BUG=chrome-os-partner:60821
TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot,
check the SSDT dump and verify WRDS and EWRD structures.
Change-Id: I3dc4219676f1b4cfb108d15ec25f4c992e0367e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3dea69a487
Original-Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17959
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428260
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5aadea9d76
Original-BUG=chrome-os-partner:61803
Original-BRANCH=reef
Original-TEST=emerge-pyro coreboot
Original-Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18086
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I63d4092acbb26602df9c501b8d87bfb3169ee79d
Reviewed-on: https://chromium-review.googlesource.com/428259
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This updates the configuration for ARM CrOS devices (nyans and veyrons)
by using the CHROMEOS Kconfig option, thus reducing the number of
options to select. It also brings proper serial console support.
BUG=none
BRANCH=none
TEST=none
Change-Id: I455b66801c3518319e078aa63d63b515ee80cd22
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a9ec36fd4
Original-Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/17928
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428258
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
mvmap2315_reset() is called from locations where we're checking for NULL
pointers. Because coverity can't tell from the code that the functions
are not returning, it's showing errors of accessing pointers after
we've determined that they're invalid.
Mark it as noreturn, and add a loop in case the reset isn't on the
next instruction. This probably isn't needed, but shouldn't hurt.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icabde50124ed8206a0a114cd10002ef81a770f57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3051cd9265
Original-Found-by: Coverity Scan #1362809
Original-Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18103
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428257
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Other chips dump tco_status here if it wasn't handled, which makes
sense.
tco_sts can't be zero here, because the call would have already returned
if it were. Also, dump_tco_status wouldn't print anything if tco_sts
were zero.
This will still only print the debug information if DEBUG_SMI is
enabled in Kconfig, so in general, this change won't have much of an
effect on anything.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icfe18802dfe054409e3e0ca111a3a0c272ab2a2d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e3b858888
Original-Found-by: Coverity Scan #1229598
Original-Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18101
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428256
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
This should always have been an and, not an or.
The only way this would happen is if no GPIOs were getting configured,
so we shouldn't ever have a NULL here, but if we did, GPIOs would
be randomly configured, which would have 'interesting' results.
BUG=none
BRANCH=none
TEST=none
Change-Id: I480ac3acde34c2f3d44424a001065f37a2428d72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e4cb50420
Original-Found-by: Coverity Scan #1229633 & 1229632
Original-Change-Id: If123372658383f84279738e1186425beba3208ca
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18095
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428255
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
On Chrome OS devices that use TPM2 parts the platform hierarchy
is disabled by the boot loader, depthcharge. Since the bootloader
isn't involved in resuming a suspended machine there's no equivalent
action in coreboot to disable the platform hierarchy. Therefore, to
ensure consistent state in resume the platform hierarchy in the TPM2
needs to be disabled as well. For systems that resume using the
firmware the platform hierarchy is disabled when utilizing
TPM2 devices.
BUG=chrome-os-partner:61097
BRANCH=reef
TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start
trunksd' shows that phEnable is 0.
Change-Id: I144a36d8ff10ce92d3de0b26d924fd85468a9764
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f56c7787ba
Original-Change-Id: I060252f338c8fd68389273224ee58caa99881de8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18096
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428254
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The orphaned Tab_TrefT_k causes a failure to build due to
an unused variable warning on GCC 6. Remove this variable.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib66ec10a6babbc59814ed51d244af2ef75306b96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 17b66c3846
Original-Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18094
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/428253
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic4a743faf8fdcc7b26c9fe2ed43ce10a539f79e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fb64d0b88
Original-Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Original-Found-by: Coverity Scan #1291162
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/428252
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Build issues were somehow overlooked in commit
ed840023a8:
1. hexstrtobin is not defined (needs the lib.h);
2. coreboot default compiler doesn't like variable initialization
within for loop.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: Iaf8ccf86e3b53fac481f28356d838728149d3e49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id:
Original-Change-Id: I85b1394956ceb9b64e1b72f9f71982b6205d5a99
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Original-Commit-Id: feb4ef6d92
Original-Original-Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0
Original-Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Original-Reviewed-on: https://review.coreboot.org/18076
Original-Original-Tested-by: build bot (Jenkins)
Original-Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428251
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions. Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0a31097c60af1fa050b6794ed5d631a7aa4c0d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 590a3e1f6c
Original-Found-by: Coverity Scan #1347337
Original-Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18079
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/428249
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The FSP 2.0 change broke the logic for determining whether or not
to execute the GOP binary. Modify the FSP 2.0 code to do the right
thing and check for display_init_required() before passing VBT into
FSP and the GOP binary.
BUG=chrome-os-partner:61726
TEST=disable developer mode and ensure FSP does not run GOP
Change-Id: I9c607739eb791bbb4351059d2528c194328f6b95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d48410631
Original-Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18084
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/428248
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing DRAM clock speed to configuration value logic contained
an error resulting in a theoretical out of bounds read. While this
would not be hit on real hardware, it was prudent to clean up the
logic to avoid the associated Coverity warning.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57792539445f2026f5c88445ebce1e0ae026c60a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f9468f019
Original-Found-by: Coverity Scan #1347353
Original-Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18073
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/428245
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended. Fix the calls to the maximum read latency
training function.
BUG=none
BRANCH=none
TEST=none
Change-Id: I020e2cf73a59d31d83ce63392f39419e714f0fd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fa624784e
Original-Found-by: Coverity Scan #1347354
Original-Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18072
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428244
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Fix SPI flash ops regressions after commit:
c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING
When spi_flash_cmd() is called with argument response==NULL,
only send out command without reading back the response.
BUG=none
BRANCH=none
TEST=none
Change-Id: I618a26349ff21649cc908562d19d8e367f2e24bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 85b2b27e33
Original-Change-Id: I28a94f208b4a1983d45d69d46db41391e267891d
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18082
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/428242
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The critical delay delta was incorrectly specified as an
unsigned short. Use a signed short instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id41a1e68498d987db502f082a9402e34f5aa0c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5153cbfeb3
Original-Found-by: Coverity Scan #1347355
Original-Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18071
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428241
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing logic to set up CsMux45 used an incorrect mask
and comparison value due to a copy + paste editing error.
Use the correct mask and comparison value for the last two
values.
BUG=none
BRANCH=none
TEST=none
Change-Id: I07b094e8d748ee30d6147f6e183522705a0a8b4f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf1cb5b2d4
Original-Found-by: Coverity Scan #1347385
Original-Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18070
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/428240
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The existing code waiting for northbridge P-state transitions
contained a logical error preventing correct operation. Fix
the logical error and force coreboot to wait for the P-state
transitions per the BKDG.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibc395db02f423594f4c1c0bd219538f9318fb819
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aeaabd3fa3
Original-Found-by: Coverity Scan #1347388
Original-Change-Id: I35f498c836db1439734abe684354c18c8e160368
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18069
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/428239
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
The code to set the igd frequencies is written with the mobile version
of the 945 chipset in mind and seems to cause cause strange igd
related problems on the desktop versions.
Some possible problems are:
* on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
* on 800MHz fsb CPU memtest results vary a lot;
* since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
variant board scheme" that does not affect this northbridge, the
display shows garbage as soon as Linux (4.8) modesets the display.
A fix is to hardcode the core display and render clocks to their
maximum, potentially also improving graphical performance.
Vendor bios on all boards in coreboot with this northbridge have the
same value in this PCI config address.
TESTED on P5GC-MX (display works fine again in Linux) and
user reports of it making GA-945GCM-S2L run more stable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I47a2d4b2a12981d8c644108499230bc92769f1f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1853781748
Original-Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/17981
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/427477
On AMD DDR3 platforms, the upper DQMask was incorrectly
calculated, leading to undefined behaviour and possible
DRAM training faults. Use the correct calculation for
the upper DQMask.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibefa976ee627cf5d2515bf3aa52f65795dc6e303
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 21b01b80d6
Original-Found-by: Coverity Scan #1347394#1347393
Original-Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-on: https://review.coreboot.org/18068
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/427476
