does not compile, but this needed fixing anyway.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1132 f3766cd6-281f-0410-b1cd-43a5c92072e9
A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach
the NAND controller. Only NAND controller, as the only DIVIL component that is
allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals
(that are separate GLIU devices outside DIVIL component) can use addresses above
that limit (see in-code comment for details).
In combination with a new VSA2 version 1.02 or newer, this makes NAND flash
finally work in coreboot v3.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1125 f3766cd6-281f-0410-b1cd-43a5c92072e9
Trivial: constant currently not used anywhere.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1124 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1123 f3766cd6-281f-0410-b1cd-43a5c92072e9
The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better.
It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late
before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2
before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it
enabled in VSA2.
It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch,
but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the
VSA2 bug suggests something further will still need fixing. There are also more potential opportunities
to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup
actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1113 f3766cd6-281f-0410-b1cd-43a5c92072e9
src/northbridge/intel/i945/ich7.h:
Thanks to Uwe Hermann for spotting this typo.
src/southbridge/intel/i82801gx/i82801gx_lpc.c:
The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).
The ICH7 needs a different init code. Drop the non-working code for now.
src/southbridge/intel/i82801gx/i82801gx.h:
Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.
Build-tested with kontron/986lcd-m.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1107 f3766cd6-281f-0410-b1cd-43a5c92072e9
Peter has some valid points that need to be addressed in the future. See his
Ack message.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1100 f3766cd6-281f-0410-b1cd-43a5c92072e9
offset_pciio and an offset_io. This makes it easier to port things from v2.
It also updates mcp55 and some whitespace there.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1099 f3766cd6-281f-0410-b1cd-43a5c92072e9
file-by-file changes:
dts:
There are no bus devices, remove it. Add the northbridge devices.
Fix susbsytem_vendor and subsystem_device.
southbridge/intel/i82371eb/ide:
Make the ide enabled by default.
northbridge/intel/i440bxemulation/i440bx.c:
1. Split ops into domain and northbridge
A. Domain should have bus ops, scan_bus, etc.
B. Northbridge should have ops for its own registers.
In this case it only needs read and set resources.
functions:
i440bx_read_resources - set up the IO and VGA resources. VGA is fixed.
i440bx_ram_resources - this should be called after resource assignment.
i440bx_set_resources - call pci_set_resources then i440bx_ram_resources.
i440bx_domain_read_resources - Set up system-wide resources, and
reserve space for the local APIC. I put the IOAPIC here too,
but it belongs somewhere in the southbridge.
i440bx_domain_set_resources - Mark the domain-specific resources as
stored (In a real device you'd probably need to set some
registers here.) Call phase4_set_resources for children.
southbridge/intel/i82371eb/i82371eb.c:
1. Add ISA read and set resources to reserve legacy IO space.
- Note that since it's subtractively decoded, it doesn't need
to be stored anywhere. It needs to be marked stored so
pci_set_resource doesn't try to store it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9
This patch fixes up geode for the new resource allocator. This is the
bare minimum. I think the functions of the northbridge should be split based
on whether they are domain-specific or not.
southbridge/amd/cs5536/cs5536.c:
Change read resources to add a fixed IO resource for legacy decoding.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1091 f3766cd6-281f-0410-b1cd-43a5c92072e9
This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
disk and attempt to boot a linux kernel.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Moves non-DRAM early init code out of initram and into stage1, where
it should have been in the first place
* Fixes an issue with GP3 timer causing system reboot (possibly not
present in current svn, but was present in my local copy)
* Fixes serial garbage from stage1 on jetway j7f2
* Fixes ROM mapping for flash > 512k on vt8237
* Makes a couple minor whitespace changes
* Moves some function prototypes to the headers where they belong
* Nukes some phase2 hackery that belongs in phase4 (eventually)
* Comments out early_mtrr_init() for via/epia-cn, this breaks booting on
jetway j7f2
* Moves troublesome SATA init code into stage1 - change of device class
hangs coreboot
* Gets to vt8237 IDE phase6 init and dies on jetway/j7f2:
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:10.1 init.
Primary IDE interface enabled
Secondary IDE interface enabled
<hang>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1070 f3766cd6-281f-0410-b1cd-43a5c92072e9
hardware and have a specific size.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
Two unused variables, an incorrect pointer type, and two printf format
warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1068 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1061 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1052 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1051 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1050 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/libsmbus.c
Corrections (minor)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1_debug.c
don't include statictree.c
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Index: mainboard/kontron/986lcd-m/initram.c
Add functions. This is all about splitting auto.c into stage1 and initram.
stage1 is very small and limited.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1049 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
that it uses the correct functions. Using the device functions on the bridge
was not so good for it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1046 f3766cd6-281f-0410-b1cd-43a5c92072e9
Parts of this patch (southbridge/intel/i82801gx/smi.c) were
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
The rest is
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1031 f3766cd6-281f-0410-b1cd-43a5c92072e9
/home/rminnich/coreboot-v3/build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: dual_channel_slew_group_lookup.3242 single_channel_slew_group_lookup.3243
and
/home/rminnich/coreboot-v3/southbridge/intel/i82801gx/smbus.c:34: error: conflicting types for ‘smbus_read_byte’
include/device/smbus.h:56: error: previous declaration of ‘smbus_read_byte’ was here
we are working these. The second is much harder than it seems.
It concerns whether we put i2c devices (i.e. DRAM spd SEEPROMS) in the dts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1026 f3766cd6-281f-0410-b1cd-43a5c92072e9
Comment out not-yet-supplied initialize_cpus.
Fix missing ; in smbus.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1025 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make statics non-static (we don't do buildrom any more)
Index: northbridge/intel/i945/raminit.c
remove snarf-o that left k8 in (I used wrong script I guess?)
Index: southbridge/intel/i82801gx/stage1_smbus.c
static to global
Index: mainboard/kontron/986lcd-m/stage1.c
Remove functions that have to be in initram.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1020 f3766cd6-281f-0410-b1cd-43a5c92072e9
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!
Index: arch/x86/via/stage1.c
Add empty stop_ap()
Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1017 f3766cd6-281f-0410-b1cd-43a5c92072e9
Why? Because the board doesn't use ide support. So you can't compile that in, it's not in the dts.
the mainboard Makefile picks the southbridge .c's to use.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1009 f3766cd6-281f-0410-b1cd-43a5c92072e9
and keep getting called away ... waiting for 1024 procs takes patience!)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1008 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1007 f3766cd6-281f-0410-b1cd-43a5c92072e9
cpu setup is nonexistent. No car either. Work remains ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1000 f3766cd6-281f-0410-b1cd-43a5c92072e9
This actually starts to get compile errors, instead of config errors.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@994 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is from v2. Once again, the pattern:
- save the chip name for the common enable parts, hence i82801gx.c
- remove the leading i82801_ from most other bits, since we compile
in different directories now
- Every device of a type has a distinct .c file (e.g. pcie.c)
- Each device of a type may be realized in more than one bit of silicon,
and have more than one set of operations, although code is common.
These are placed into distinct operations structs (see pcie.c)
- for every distinct device, there is a .dts file.
This set of rules makes for simple cross-part standardization of code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@991 f3766cd6-281f-0410-b1cd-43a5c92072e9
Modify chipset_flash_setup to support enabling NAND flash on other locations
than CS0, by making enable_ide_nand_flash have a non-boolean meaning where zero
means no NAND (IDE), and 1 through 4 gives the one-based chip select array
location (so 1 means CS0, 2 means CS1, 3 means CS2 and 4 means CS3, as chip
select notation is zero-based).
This loses the code for supporting more than one NAND chip select or different
ones than FLASH_MEM_4K, but these couldn't be supported before anyway, because
that is board specific, but the supporting structure was a static const struct
in generic southbridge specific code.
This support should be instead implemented via the device tree dts files.
Enables NAND on ArtecGroup DBE61 and DBE62 on CS1, as that's where it is.
The end result is that these mainboards can now boot off of NAND with FILO
without local modifications to the previously existing southbridge specific
static const struct that had no chance of being upstreamed as it would break
all other CS5536 NAND boards that have it on CS0.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@985 f3766cd6-281f-0410-b1cd-43a5c92072e9
Does not yet build
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@967 f3766cd6-281f-0410-b1cd-43a5c92072e9
Most substantive change is getting rid of 'initialized', which was only
ever needed in v2 due to an implementation mistake.
With Uwe's comments taken into account,
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@961 f3766cd6-281f-0410-b1cd-43a5c92072e9
