147 commits

Author	SHA1	Message	Date
Unknown W. Brackets	4e41f83ecc	riscv: Centralize IR reg cache metadata checks. ... These are all largely the same between backends.	2023-08-17 23:03:31 -07:00
Unknown W. Brackets	ebab0e1591	riscv: Centralize reg allocation.	2023-08-17 18:50:33 -07:00
Unknown W. Brackets	b30daa5760	riscv: Centralize state of regcaches.	2023-08-15 21:51:38 -07:00
Henrik Rydgård	a7bc70834c	Merge pull request #17907 from unknownbrackets/riscv-minor ... riscv: Implement vs2i	2023-08-14 07:41:45 +02:00
Unknown W. Brackets	52cc38bf2a	riscv: Implement vs2i.	2023-08-13 18:27:19 -07:00
Henrik Rydgård	5dcd14b17a	Merge pull request #17901 from unknownbrackets/riscv-disasm ... riscv: Add debug log of block disasm	2023-08-13 21:07:37 +02:00
Unknown W. Brackets	f03cd0b2ad	Merge pull request #17899 from unknownbrackets/riscv-minor ... Minor RISC-V cleanups, frame profiler fix	2023-08-13 11:19:42 -07:00
Henrik Rydgård	d6cdb6e5d9	Merge pull request #17900 from unknownbrackets/irjit-vsgelt ... irjit: Implement vsge/vslt	2023-08-13 19:59:14 +02:00
Unknown W. Brackets	2b36e0a625	irjit: ZeroFpCond -> FpCondFromReg. ... We already have a zero reg, so this is more useful and symmetrical.	2023-08-13 10:40:47 -07:00
Unknown W. Brackets	2bb67db43c	riscv: Switch to the logBlocks model for disasm.	2023-08-13 10:37:21 -07:00
Unknown W. Brackets	8c036a889d	riscv: Add debug log of block disasm.	2023-08-13 10:32:04 -07:00
Unknown W. Brackets	7cc6c5fa62	riscv: Fix load error w/o pointerify.	2023-08-13 10:20:28 -07:00
Unknown W. Brackets	be938a850b	riscv: Remove FMul safety check. ... Let's just see if everything's right, this bloats multiplies a lot. Doesn't seem to impact perf a lot, though.	2023-08-13 10:20:20 -07:00
Unknown W. Brackets	fcc90095f7	riscv: Enable block linking.	2023-08-12 09:37:02 -07:00
Unknown W. Brackets	247788806a	irjit: Add direct helper for start PC. ... It's annoying always fetching length too.	2023-08-12 09:37:02 -07:00
Unknown W. Brackets	b3cdf06c5a	riscv: Write fixup on block invalidation.	2023-08-12 09:37:02 -07:00
Unknown W. Brackets	3757ebca2d	irjit: Invalidate/finalize target blocks. ... Doesn't actually do anything yet, but adds plumbing.	2023-08-12 09:37:02 -07:00
Henrik Rydgård	2342c4522c	Merge pull request #17875 from unknownbrackets/riscv-jit ... RISC-V: Implement a few more ops	2023-08-09 09:30:15 +02:00
Unknown W. Brackets	2c13b6d973	riscv: Implement vc2i.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	4b9011e475	riscv: Reduce call bloat using temps.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	ddf3d02a3c	riscv: Implement vi2uc.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	268adf1aa1	riscv: Implement scaled float/int convert.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	0b4e7d60f9	riscv: Implement ReverseBits in jit.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	ad4cbbab8e	riscv: Don't cache mipState on backend. ... Bad sign if we're trying to use it, anyway.	2023-08-08 23:17:32 -07:00
Unknown W. Brackets	1a92027810	riscv: Make Vec4Shuffle overlap safe.	2023-08-08 23:00:45 -07:00
Unknown W. Brackets	79ca880ac7	irjit: Implement vqmul, add Vec4Blend. ... Should be useful more places.	2023-08-06 13:38:00 -07:00
Unknown W. Brackets	93e3d35f5d	irjit: Move more to IRNativeBackend, split.	2023-08-06 00:16:43 -07:00
Unknown W. Brackets	691799a0ca	irjit: Centralize native jit compile dispatch.	2023-08-03 23:14:58 -07:00
Unknown W. Brackets	c24dca12bb	Build: Fix link issue for rv64 disasm.	2023-07-30 16:06:55 -07:00
Unknown W. Brackets	b03398a46c	Merge pull request #17815 from unknownbrackets/riscv-jit ... riscv: Spill registers more intelligently	2023-07-30 14:49:37 -07:00
Henrik Rydgård	fa2b831dbc	Merge pull request #17814 from unknownbrackets/riscv-jit-debug ... riscv: Implement block debug interface	2023-07-30 23:42:14 +02:00
Henrik Rydgård	fa558b5b71	Merge pull request #17813 from unknownbrackets/riscv-jit-fixes ... Fix some typos and mistakes in RISC-V jit	2023-07-30 23:41:13 +02:00
Unknown W. Brackets	f870271011	riscv: Spill registers more intelligently.	2023-07-30 14:24:12 -07:00
Unknown W. Brackets	020706f545	riscv: Implement float saturate clamping.	2023-07-30 14:24:12 -07:00
Unknown W. Brackets	45d44c1d4f	riscv: Implement block debug interface. ... This gives us the target disasm in jit compare, bloat, etc.	2023-07-30 14:21:43 -07:00
Unknown W. Brackets	5ef4b2b5fa	riscv: Fix assert when flushing not mapped reg.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	e34736fbb2	riscv: Reduce norms in Slt/Sltu overlap cases. ... We can skip an SEXT.W in common cases where the dest and src overlap.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	d1dc346899	riscv: Fix pointer add/sub.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	09f3842a32	riscv: Fix VFPU compare typos.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	5db6b11ef2	irjit: Cleanup self-fmovs. ... These were sometimes getting emitted.	2023-07-30 14:16:17 -07:00
Unknown W. Brackets	c24e3ef831	riscv: Implement ll/sc.	2023-07-30 00:45:51 -07:00
Unknown W. Brackets	26a527bdf8	riscv: Implement float/int conversion.	2023-07-30 00:45:51 -07:00
Henrik Rydgård	b93275bb35	Merge pull request #17800 from unknownbrackets/riscv-jit ... More RISC-V jit ops	2023-07-30 09:26:22 +02:00
Henrik Rydgård	180bda6f6b	Merge pull request #17799 from unknownbrackets/irjit-lsu ... Add ll/sc to IR and x86jit	2023-07-30 09:15:55 +02:00
Unknown W. Brackets	0036f3c494	riscv: Implement FMin/FMax.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	8e8081c686	riscv: Implement VFPU compares.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	9c9330a207	riscv: Implement float conditional move.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	70ff18a463	riscv: Implement count leading zeros.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	a5671bc716	riscv: Add simple debug log of missed ops.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	6d4fb949c2	riscv: Implement float compare ops.	2023-07-29 19:02:15 -07:00