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irjit: Centralize native jit compile dispatch.

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This commit is contained in:
Unknown W. Brackets 2023-08-03 23:05:10 -07:00
parent 0d0029fc9d
commit 691799a0ca
11 changed files with 561 additions and 430 deletions
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2
CMakeLists.txt
View file

@ -1554,6 +1554,8 @@ set(CoreExtra ${CoreExtra}
Core/MIPS/IR/IRInterpreter.h
Core/MIPS/IR/IRJit.cpp
Core/MIPS/IR/IRJit.h
Core/MIPS/IR/IRNativeCommon.cpp
Core/MIPS/IR/IRNativeCommon.h
Core/MIPS/IR/IRPassSimplify.cpp
Core/MIPS/IR/IRPassSimplify.h
Core/MIPS/IR/IRRegCache.cpp

2
Core/Core.vcxproj
View file

@ -591,6 +591,7 @@
<ClCompile Include="MIPS\IR\IRInst.cpp" />
<ClCompile Include="MIPS\IR\IRInterpreter.cpp" />
<ClCompile Include="MIPS\IR\IRJit.cpp" />
<ClCompile Include="MIPS\IR\IRNativeCommon.cpp" />
<ClCompile Include="MIPS\IR\IRPassSimplify.cpp" />
<ClCompile Include="MIPS\IR\IRRegCache.cpp" />
<ClCompile Include="MIPS\MIPSVFPUFallbacks.cpp" />
@ -1170,6 +1171,7 @@
<ClInclude Include="MIPS\IR\IRInst.h" />
<ClInclude Include="MIPS\IR\IRInterpreter.h" />
<ClInclude Include="MIPS\IR\IRJit.h" />
<ClInclude Include="MIPS\IR\IRNativeCommon.h" />
<ClInclude Include="MIPS\IR\IRPassSimplify.h" />
<ClInclude Include="MIPS\IR\IRRegCache.h" />
<ClInclude Include="MIPS\MIPSVFPUFallbacks.h" />

6
Core/Core.vcxproj.filters
View file

@ -1240,6 +1240,9 @@
<ClCompile Include="MIPS\IR\IRAnalysis.cpp">
<Filter>MIPS\IR</Filter>
</ClCompile>
<ClCompile Include="MIPS\IR\IRNativeCommon.cpp">
<Filter>MIPS\IR</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="ELF\ElfReader.h">
@ -1998,6 +2001,9 @@
<ClInclude Include="MIPS\IR\IRAnalysis.h">
<Filter>MIPS\IR</Filter>
</ClInclude>
<ClInclude Include="MIPS\IR\IRNativeCommon.h">
<Filter>MIPS\IR</Filter>
</ClInclude>
</ItemGroup>
<ItemGroup>
<None Include="..\LICENSE.TXT" />

398
Core/MIPS/IR/IRNativeCommon.cpp Normal file
View file

@ -0,0 +1,398 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Common/Profiler/Profiler.h"
#include "Core/MIPS/IR/IRNativeCommon.h"
using namespace MIPSComp;
namespace MIPSComp {
void IRNativeBackend::CompileIRInst(IRInst inst) {
switch (inst.op) {
case IROp::Nop:
break;
case IROp::SetConst:
case IROp::SetConstF:
case IROp::Downcount:
case IROp::SetPC:
case IROp::SetPCConst:
CompIR_Basic(inst);
break;
case IROp::Add:
case IROp::Sub:
case IROp::AddConst:
case IROp::SubConst:
case IROp::Neg:
CompIR_Arith(inst);
break;
case IROp::And:
case IROp::Or:
case IROp::Xor:
case IROp::AndConst:
case IROp::OrConst:
case IROp::XorConst:
case IROp::Not:
CompIR_Logic(inst);
break;
case IROp::Mov:
case IROp::Ext8to32:
case IROp::Ext16to32:
CompIR_Assign(inst);
break;
case IROp::ReverseBits:
case IROp::BSwap16:
case IROp::BSwap32:
case IROp::Clz:
CompIR_Bits(inst);
break;
case IROp::Shl:
case IROp::Shr:
case IROp::Sar:
case IROp::Ror:
case IROp::ShlImm:
case IROp::ShrImm:
case IROp::SarImm:
case IROp::RorImm:
CompIR_Shift(inst);
break;
case IROp::Slt:
case IROp::SltConst:
case IROp::SltU:
case IROp::SltUConst:
CompIR_Compare(inst);
break;
case IROp::MovZ:
case IROp::MovNZ:
case IROp::Max:
case IROp::Min:
CompIR_CondAssign(inst);
break;
case IROp::MtLo:
case IROp::MtHi:
case IROp::MfLo:
case IROp::MfHi:
CompIR_HiLo(inst);
break;
case IROp::Mult:
case IROp::MultU:
case IROp::Madd:
case IROp::MaddU:
case IROp::Msub:
case IROp::MsubU:
CompIR_Mult(inst);
break;
case IROp::Div:
case IROp::DivU:
CompIR_Div(inst);
break;
case IROp::Load8:
case IROp::Load8Ext:
case IROp::Load16:
case IROp::Load16Ext:
case IROp::Load32:
case IROp::Load32Linked:
CompIR_Load(inst);
break;
case IROp::Load32Left:
case IROp::Load32Right:
CompIR_LoadShift(inst);
break;
case IROp::LoadFloat:
CompIR_FLoad(inst);
break;
case IROp::LoadVec4:
CompIR_VecLoad(inst);
break;
case IROp::Store8:
case IROp::Store16:
case IROp::Store32:
CompIR_Store(inst);
break;
case IROp::Store32Conditional:
CompIR_CondStore(inst);
break;
case IROp::Store32Left:
case IROp::Store32Right:
CompIR_StoreShift(inst);
break;
case IROp::StoreFloat:
CompIR_FStore(inst);
break;
case IROp::StoreVec4:
CompIR_VecStore(inst);
break;
case IROp::FAdd:
case IROp::FSub:
case IROp::FMul:
case IROp::FDiv:
case IROp::FSqrt:
case IROp::FNeg:
CompIR_FArith(inst);
break;
case IROp::FMin:
case IROp::FMax:
CompIR_FCondAssign(inst);
break;
case IROp::FMov:
case IROp::FAbs:
case IROp::FSign:
CompIR_FAssign(inst);
break;
case IROp::FRound:
case IROp::FTrunc:
case IROp::FCeil:
case IROp::FFloor:
CompIR_FRound(inst);
break;
case IROp::FCvtWS:
case IROp::FCvtSW:
case IROp::FCvtScaledWS:
case IROp::FCvtScaledSW:
CompIR_FCvt(inst);
break;
case IROp::FSat0_1:
case IROp::FSatMinus1_1:
CompIR_FSat(inst);
break;
case IROp::FCmp:
case IROp::FCmovVfpuCC:
case IROp::FCmpVfpuBit:
case IROp::FCmpVfpuAggregate:
CompIR_FCompare(inst);
break;
case IROp::RestoreRoundingMode:
case IROp::ApplyRoundingMode:
case IROp::UpdateRoundingMode:
CompIR_RoundingMode(inst);
break;
case IROp::SetCtrlVFPU:
case IROp::SetCtrlVFPUReg:
case IROp::SetCtrlVFPUFReg:
case IROp::FpCondToReg:
case IROp::ZeroFpCond:
case IROp::FpCtrlFromReg:
case IROp::FpCtrlToReg:
case IROp::VfpuCtrlToReg:
case IROp::FMovFromGPR:
case IROp::FMovToGPR:
CompIR_Transfer(inst);
break;
case IROp::Vec4Init:
case IROp::Vec4Shuffle:
case IROp::Vec4Mov:
CompIR_VecAssign(inst);
break;
case IROp::Vec4Add:
case IROp::Vec4Sub:
case IROp::Vec4Mul:
case IROp::Vec4Div:
case IROp::Vec4Scale:
case IROp::Vec4Neg:
case IROp::Vec4Abs:
CompIR_VecArith(inst);
break;
case IROp::Vec4Dot:
CompIR_VecHoriz(inst);
break;
case IROp::Vec2Unpack16To31:
case IROp::Vec2Unpack16To32:
case IROp::Vec4Unpack8To32:
case IROp::Vec4DuplicateUpperBitsAndShift1:
case IROp::Vec4Pack31To8:
case IROp::Vec4Pack32To8:
case IROp::Vec2Pack31To16:
case IROp::Vec2Pack32To16:
CompIR_VecPack(inst);
break;
case IROp::Vec4ClampToZero:
case IROp::Vec2ClampToZero:
CompIR_VecClamp(inst);
break;
case IROp::FSin:
case IROp::FCos:
case IROp::FRSqrt:
case IROp::FRecip:
case IROp::FAsin:
CompIR_FSpecial(inst);
break;
case IROp::Interpret:
CompIR_Interpret(inst);
break;
case IROp::Syscall:
case IROp::CallReplacement:
case IROp::Break:
CompIR_System(inst);
break;
case IROp::Breakpoint:
case IROp::MemoryCheck:
CompIR_Breakpoint(inst);
break;
case IROp::ValidateAddress8:
case IROp::ValidateAddress16:
case IROp::ValidateAddress32:
case IROp::ValidateAddress128:
CompIR_ValidateAddress(inst);
break;
case IROp::ExitToConst:
case IROp::ExitToReg:
case IROp::ExitToPC:
CompIR_Exit(inst);
break;
case IROp::ExitToConstIfEq:
case IROp::ExitToConstIfNeq:
case IROp::ExitToConstIfGtZ:
case IROp::ExitToConstIfGeZ:
case IROp::ExitToConstIfLtZ:
case IROp::ExitToConstIfLeZ:
case IROp::ExitToConstIfFpTrue:
case IROp::ExitToConstIfFpFalse:
CompIR_ExitIf(inst);
break;
default:
_assert_msg_(false, "Unexpected IR op %d", (int)inst.op);
CompIR_Generic(inst);
break;
}
}
} // namespace MIPSComp
IRNativeBlockCacheDebugInterface::IRNativeBlockCacheDebugInterface(IRBlockCache &irBlocks, CodeBlockCommon &codeBlock)
: irBlocks_(irBlocks), codeBlock_(codeBlock) {}
int IRNativeBlockCacheDebugInterface::GetNumBlocks() const {
return irBlocks_.GetNumBlocks();
}
int IRNativeBlockCacheDebugInterface::GetBlockNumberFromStartAddress(u32 em_address, bool realBlocksOnly) const {
return irBlocks_.GetBlockNumberFromStartAddress(em_address, realBlocksOnly);
}
void IRNativeBlockCacheDebugInterface::GetBlockCodeRange(int blockNum, int *startOffset, int *size) const {
int blockOffset = irBlocks_.GetBlock(blockNum)->GetTargetOffset();
int endOffset;
// We assume linear allocation. Maybe a bit dangerous, should always be right.
if (blockNum + 1 >= GetNumBlocks()) {
// Last block, get from current code pointer.
endOffset = (int)codeBlock_.GetOffset(codeBlock_.GetCodePtr());
} else {
endOffset = irBlocks_.GetBlock(blockNum + 1)->GetTargetOffset();
_assert_msg_(endOffset >= blockOffset, "Next block not sequential, block=%d/%08x, next=%d/%08x", blockNum, blockOffset, blockNum + 1, endOffset);
}
*startOffset = blockOffset;
*size = endOffset - blockOffset;
}
JitBlockDebugInfo IRNativeBlockCacheDebugInterface::GetBlockDebugInfo(int blockNum) const {
JitBlockDebugInfo debugInfo = irBlocks_.GetBlockDebugInfo(blockNum);
int blockOffset, codeSize;
GetBlockCodeRange(blockNum, &blockOffset, &codeSize);
// TODO: Normal entry?
const u8 *blockStart = codeBlock_.GetBasePtr() + blockOffset;
#if PPSSPP_ARCH(ARM)
debugInfo.targetDisasm = DisassembleArm2(blockStart, codeSize);
#elif PPSSPP_ARCH(ARM64)
debugInfo.targetDisasm = DisassembleArm64(blockStart, codeSize);
#elif PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
debugInfo.targetDisasm = DisassembleX86(blockStart, codeSize);
#elif PPSSPP_ARCH(RISCV64)
debugInfo.targetDisasm = DisassembleRV64(blockStart, codeSize);
#endif
return debugInfo;
}
void IRNativeBlockCacheDebugInterface::ComputeStats(BlockCacheStats &bcStats) const {
double totalBloat = 0.0;
double maxBloat = 0.0;
double minBloat = 1000000000.0;
int numBlocks = GetNumBlocks();
for (int i = 0; i < numBlocks; ++i) {
const IRBlock &b = *irBlocks_.GetBlock(i);
// Native size, not IR size.
int blockOffset, codeSize;
GetBlockCodeRange(i, &blockOffset, &codeSize);
if (codeSize == 0)
continue;
// MIPS (PSP) size.
u32 origAddr, origSize;
b.GetRange(origAddr, origSize);
double bloat = (double)codeSize / (double)origSize;
if (bloat < minBloat) {
minBloat = bloat;
bcStats.minBloatBlock = origAddr;
}
if (bloat > maxBloat) {
maxBloat = bloat;
bcStats.maxBloatBlock = origAddr;
}
totalBloat += bloat;
bcStats.bloatMap[(float)bloat] = origAddr;
}
bcStats.numBlocks = numBlocks;
bcStats.minBloat = (float)minBloat;
bcStats.maxBloat = (float)maxBloat;
bcStats.avgBloat = (float)(totalBloat / (double)numBlocks);
}

94
Core/MIPS/IR/IRNativeCommon.h Normal file
View file

@ -0,0 +1,94 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Core/MIPS/IR/IRJit.h"
#include "Core/MIPS/JitCommon/JitBlockCache.h"
class IRNativeBlockCacheDebugInterface : public JitBlockCacheDebugInterface {
public:
IRNativeBlockCacheDebugInterface(MIPSComp::IRBlockCache &irBlocks, CodeBlockCommon &codeBlock);
int GetNumBlocks() const;
int GetBlockNumberFromStartAddress(u32 em_address, bool realBlocksOnly = true) const;
JitBlockDebugInfo GetBlockDebugInfo(int blockNum) const;
void ComputeStats(BlockCacheStats &bcStats) const;
private:
void GetBlockCodeRange(int blockNum, int *startOffset, int *size) const;
MIPSComp::IRBlockCache &irBlocks_;
CodeBlockCommon &codeBlock_;
};
namespace MIPSComp {
class IRNativeBackend {
public:
virtual ~IRNativeBackend() {}
void CompileIRInst(IRInst inst);
protected:
virtual void CompIR_Arith(IRInst inst) = 0;
virtual void CompIR_Assign(IRInst inst) = 0;
virtual void CompIR_Basic(IRInst inst) = 0;
virtual void CompIR_Bits(IRInst inst) = 0;
virtual void CompIR_Breakpoint(IRInst inst) = 0;
virtual void CompIR_Compare(IRInst inst) = 0;
virtual void CompIR_CondAssign(IRInst inst) = 0;
virtual void CompIR_CondStore(IRInst inst) = 0;
virtual void CompIR_Div(IRInst inst) = 0;
virtual void CompIR_Exit(IRInst inst) = 0;
virtual void CompIR_ExitIf(IRInst inst) = 0;
virtual void CompIR_FArith(IRInst inst) = 0;
virtual void CompIR_FAssign(IRInst inst) = 0;
virtual void CompIR_FCompare(IRInst inst) = 0;
virtual void CompIR_FCondAssign(IRInst inst) = 0;
virtual void CompIR_FCvt(IRInst inst) = 0;
virtual void CompIR_FLoad(IRInst inst) = 0;
virtual void CompIR_FRound(IRInst inst) = 0;
virtual void CompIR_FSat(IRInst inst) = 0;
virtual void CompIR_FSpecial(IRInst inst) = 0;
virtual void CompIR_FStore(IRInst inst) = 0;
virtual void CompIR_Generic(IRInst inst) = 0;
virtual void CompIR_HiLo(IRInst inst) = 0;
virtual void CompIR_Interpret(IRInst inst) = 0;
virtual void CompIR_Load(IRInst inst) = 0;
virtual void CompIR_LoadShift(IRInst inst) = 0;
virtual void CompIR_Logic(IRInst inst) = 0;
virtual void CompIR_Mult(IRInst inst) = 0;
virtual void CompIR_RoundingMode(IRInst inst) = 0;
virtual void CompIR_Shift(IRInst inst) = 0;
virtual void CompIR_Store(IRInst inst) = 0;
virtual void CompIR_StoreShift(IRInst inst) = 0;
virtual void CompIR_System(IRInst inst) = 0;
virtual void CompIR_Transfer(IRInst inst) = 0;
virtual void CompIR_VecArith(IRInst inst) = 0;
virtual void CompIR_VecAssign(IRInst inst) = 0;
virtual void CompIR_VecClamp(IRInst inst) = 0;
virtual void CompIR_VecHoriz(IRInst inst) = 0;
virtual void CompIR_VecLoad(IRInst inst) = 0;
virtual void CompIR_VecPack(IRInst inst) = 0;
virtual void CompIR_VecStore(IRInst inst) = 0;
virtual void CompIR_ValidateAddress(IRInst inst) = 0;
};
class IRNativeJit : public IRJit {
public:
IRNativeJit(MIPSState *mipsState) : IRJit(mipsState) {}
};
} // namespace MIPSComp

368
Core/MIPS/RiscV/RiscVJit.cpp
View file

@ -70,7 +70,7 @@ static void LogDebugNotCompiled() {
}
RiscVJit::RiscVJit(MIPSState *mipsState)
: IRJit(mipsState), gpr(mipsState, &jo), fpr(mipsState, &jo), debugInterface_(blocks_, *this) {
: IRNativeJit(mipsState), gpr(mipsState, &jo), fpr(mipsState, &jo), debugInterface_(blocks_, *this) {
// Automatically disable incompatible options.
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
jo.enablePointerify = false;
@ -148,296 +148,6 @@ bool RiscVJit::CompileTargetBlock(IRBlock *block, int block_num, bool preload) {
return true;
}
void RiscVJit::CompileIRInst(IRInst inst) {
switch (inst.op) {
case IROp::Nop:
break;
case IROp::SetConst:
case IROp::SetConstF:
case IROp::Downcount:
case IROp::SetPC:
case IROp::SetPCConst:
CompIR_Basic(inst);
break;
case IROp::Add:
case IROp::Sub:
case IROp::AddConst:
case IROp::SubConst:
case IROp::Neg:
CompIR_Arith(inst);
break;
case IROp::And:
case IROp::Or:
case IROp::Xor:
case IROp::AndConst:
case IROp::OrConst:
case IROp::XorConst:
case IROp::Not:
CompIR_Logic(inst);
break;
case IROp::Mov:
case IROp::Ext8to32:
case IROp::Ext16to32:
CompIR_Assign(inst);
break;
case IROp::ReverseBits:
case IROp::BSwap16:
case IROp::BSwap32:
case IROp::Clz:
CompIR_Bits(inst);
break;
case IROp::Shl:
case IROp::Shr:
case IROp::Sar:
case IROp::Ror:
case IROp::ShlImm:
case IROp::ShrImm:
case IROp::SarImm:
case IROp::RorImm:
CompIR_Shift(inst);
break;
case IROp::Slt:
case IROp::SltConst:
case IROp::SltU:
case IROp::SltUConst:
CompIR_Compare(inst);
break;
case IROp::MovZ:
case IROp::MovNZ:
case IROp::Max:
case IROp::Min:
CompIR_CondAssign(inst);
break;
case IROp::MtLo:
case IROp::MtHi:
case IROp::MfLo:
case IROp::MfHi:
CompIR_HiLo(inst);
break;
case IROp::Mult:
case IROp::MultU:
case IROp::Madd:
case IROp::MaddU:
case IROp::Msub:
case IROp::MsubU:
CompIR_Mult(inst);
break;
case IROp::Div:
case IROp::DivU:
CompIR_Div(inst);
break;
case IROp::Load8:
case IROp::Load8Ext:
case IROp::Load16:
case IROp::Load16Ext:
case IROp::Load32:
case IROp::Load32Linked:
CompIR_Load(inst);
break;
case IROp::Load32Left:
case IROp::Load32Right:
CompIR_LoadShift(inst);
break;
case IROp::LoadFloat:
CompIR_FLoad(inst);
break;
case IROp::LoadVec4:
CompIR_VecLoad(inst);
break;
case IROp::Store8:
case IROp::Store16:
case IROp::Store32:
CompIR_Store(inst);
break;
case IROp::Store32Conditional:
CompIR_CondStore(inst);
break;
case IROp::Store32Left:
case IROp::Store32Right:
CompIR_StoreShift(inst);
break;
case IROp::StoreFloat:
CompIR_FStore(inst);
break;
case IROp::StoreVec4:
CompIR_VecStore(inst);
break;
case IROp::FAdd:
case IROp::FSub:
case IROp::FMul:
case IROp::FDiv:
case IROp::FSqrt:
case IROp::FNeg:
CompIR_FArith(inst);
break;
case IROp::FMin:
case IROp::FMax:
CompIR_FCondAssign(inst);
break;
case IROp::FMov:
case IROp::FAbs:
case IROp::FSign:
CompIR_FAssign(inst);
break;
case IROp::FRound:
case IROp::FTrunc:
case IROp::FCeil:
case IROp::FFloor:
CompIR_FRound(inst);
break;
case IROp::FCvtWS:
case IROp::FCvtSW:
case IROp::FCvtScaledWS:
case IROp::FCvtScaledSW:
CompIR_FCvt(inst);
break;
case IROp::FSat0_1:
case IROp::FSatMinus1_1:
CompIR_FSat(inst);
break;
case IROp::FCmp:
case IROp::FCmovVfpuCC:
case IROp::FCmpVfpuBit:
case IROp::FCmpVfpuAggregate:
CompIR_FCompare(inst);
break;
case IROp::RestoreRoundingMode:
case IROp::ApplyRoundingMode:
case IROp::UpdateRoundingMode:
CompIR_RoundingMode(inst);
break;
case IROp::SetCtrlVFPU:
case IROp::SetCtrlVFPUReg:
case IROp::SetCtrlVFPUFReg:
case IROp::FpCondToReg:
case IROp::ZeroFpCond:
case IROp::FpCtrlFromReg:
case IROp::FpCtrlToReg:
case IROp::VfpuCtrlToReg:
case IROp::FMovFromGPR:
case IROp::FMovToGPR:
CompIR_Transfer(inst);
break;
case IROp::Vec4Init:
case IROp::Vec4Shuffle:
case IROp::Vec4Mov:
CompIR_VecAssign(inst);
break;
case IROp::Vec4Add:
case IROp::Vec4Sub:
case IROp::Vec4Mul:
case IROp::Vec4Div:
case IROp::Vec4Scale:
case IROp::Vec4Neg:
case IROp::Vec4Abs:
CompIR_VecArith(inst);
break;
case IROp::Vec4Dot:
CompIR_VecHoriz(inst);
break;
case IROp::Vec2Unpack16To31:
case IROp::Vec2Unpack16To32:
case IROp::Vec4Unpack8To32:
case IROp::Vec4DuplicateUpperBitsAndShift1:
case IROp::Vec4Pack31To8:
case IROp::Vec4Pack32To8:
case IROp::Vec2Pack31To16:
case IROp::Vec2Pack32To16:
CompIR_VecPack(inst);
break;
case IROp::Vec4ClampToZero:
case IROp::Vec2ClampToZero:
CompIR_VecClamp(inst);
break;
case IROp::FSin:
case IROp::FCos:
case IROp::FRSqrt:
case IROp::FRecip:
case IROp::FAsin:
CompIR_FSpecial(inst);
break;
case IROp::Interpret:
CompIR_Interpret(inst);
break;
case IROp::Syscall:
case IROp::CallReplacement:
case IROp::Break:
CompIR_System(inst);
break;
case IROp::Breakpoint:
case IROp::MemoryCheck:
CompIR_Breakpoint(inst);
break;
case IROp::ValidateAddress8:
case IROp::ValidateAddress16:
case IROp::ValidateAddress32:
case IROp::ValidateAddress128:
CompIR_ValidateAddress(inst);
break;
case IROp::ExitToConst:
case IROp::ExitToReg:
case IROp::ExitToPC:
CompIR_Exit(inst);
break;
case IROp::ExitToConstIfEq:
case IROp::ExitToConstIfNeq:
case IROp::ExitToConstIfGtZ:
case IROp::ExitToConstIfGeZ:
case IROp::ExitToConstIfLtZ:
case IROp::ExitToConstIfLeZ:
case IROp::ExitToConstIfFpTrue:
case IROp::ExitToConstIfFpFalse:
CompIR_ExitIf(inst);
break;
default:
_assert_msg_(false, "Unexpected IR op %d", (int)inst.op);
CompIR_Generic(inst);
break;
}
}
static u32 DoIRInst(uint64_t value) {
IRInst inst;
memcpy(&inst, &value, sizeof(inst));
@ -562,7 +272,7 @@ const u8 *RiscVJit::GetCrashHandler() const {
}
void RiscVJit::ClearCache() {
IRJit::ClearCache();
IRNativeJit::ClearCache();
ClearCodeSpace(jitStartOffset_);
FlushIcacheSection(region + jitStartOffset_, region + region_size - jitStartOffset_);
@ -622,78 +332,4 @@ RiscVReg RiscVJit::NormalizeR(IRRegIndex rs, IRRegIndex rd, RiscVReg tempReg) {
}
}
RiscVBlockCacheDebugInterface::RiscVBlockCacheDebugInterface(IRBlockCache &irBlocks, RiscVJit &jit)
: irBlocks_(irBlocks), jit_(jit) {}
int RiscVBlockCacheDebugInterface::GetNumBlocks() const {
return irBlocks_.GetNumBlocks();
}
int RiscVBlockCacheDebugInterface::GetBlockNumberFromStartAddress(u32 em_address, bool realBlocksOnly) const {
return irBlocks_.GetBlockNumberFromStartAddress(em_address, realBlocksOnly);
}
void RiscVBlockCacheDebugInterface::GetBlockCodeRange(int blockNum, int *startOffset, int *size) const {
int blockOffset = irBlocks_.GetBlock(blockNum)->GetTargetOffset();
int endOffset;
// We assume linear allocation. Maybe a bit dangerous, should always be right.
if (blockNum + 1 >= GetNumBlocks()) {
// Last block, get from current code pointer.
endOffset = (int)jit_.GetOffset(jit_.GetCodePointer());
} else {
endOffset = irBlocks_.GetBlock(blockNum + 1)->GetTargetOffset();
_assert_msg_(endOffset >= blockOffset, "Next block not sequential, block=%d/%08x, next=%d/%08x", blockNum, blockOffset, blockNum + 1, endOffset);
}
*startOffset = blockOffset;
*size = endOffset - blockOffset;
}
JitBlockDebugInfo RiscVBlockCacheDebugInterface::GetBlockDebugInfo(int blockNum) const {
JitBlockDebugInfo debugInfo = irBlocks_.GetBlockDebugInfo(blockNum);
#if PPSSPP_ARCH(RISCV64)
int blockOffset, codeSize;
GetBlockCodeRange(blockNum, &blockOffset, &codeSize);
debugInfo.targetDisasm = DisassembleRV64(jit_.GetBasePtr() + blockOffset, codeSize);
#endif
return debugInfo;
}
void RiscVBlockCacheDebugInterface::ComputeStats(BlockCacheStats &bcStats) const {
double totalBloat = 0.0;
double maxBloat = 0.0;
double minBloat = 1000000000.0;
int numBlocks = GetNumBlocks();
for (int i = 0; i < numBlocks; ++i) {
const IRBlock &b = *irBlocks_.GetBlock(i);
// RISC-V (jit) size.
int blockOffset, codeSize;
GetBlockCodeRange(i, &blockOffset, &codeSize);
if (codeSize == 0)
continue;
// MIPS (PSP) size.
u32 origAddr, mipsBytes;
b.GetRange(origAddr, mipsBytes);
double bloat = (double)codeSize / (double)mipsBytes;
if (bloat < minBloat) {
minBloat = bloat;
bcStats.minBloatBlock = origAddr;
}
if (bloat > maxBloat) {
maxBloat = bloat;
bcStats.maxBloatBlock = origAddr;
}
totalBloat += bloat;
bcStats.bloatMap[bloat] = origAddr;
}
bcStats.numBlocks = numBlocks;
bcStats.minBloat = minBloat;
bcStats.maxBloat = maxBloat;
bcStats.avgBloat = totalBloat / (double)numBlocks;
}
} // namespace MIPSComp

109
Core/MIPS/RiscV/RiscVJit.h
View file

@ -21,6 +21,7 @@
#include <vector>
#include "Common/RiscVEmitter.h"
#include "Core/MIPS/IR/IRJit.h"
#include "Core/MIPS/IR/IRNativeCommon.h"
#include "Core/MIPS/JitCommon/JitState.h"
#include "Core/MIPS/JitCommon/JitCommon.h"
#include "Core/MIPS/RiscV/RiscVRegCache.h"
@ -28,24 +29,8 @@
namespace MIPSComp {
class RiscVJit;
class RiscVBlockCacheDebugInterface : public JitBlockCacheDebugInterface {
public:
RiscVBlockCacheDebugInterface(IRBlockCache &irBlocks, RiscVJit &jit);
int GetNumBlocks() const;
int GetBlockNumberFromStartAddress(u32 em_address, bool realBlocksOnly = true) const;
JitBlockDebugInfo GetBlockDebugInfo(int blockNum) const;
void ComputeStats(BlockCacheStats &bcStats) const;
private:
void GetBlockCodeRange(int blockNum, int *startOffset, int *size) const;
IRBlockCache &irBlocks_;
RiscVJit &jit_;
};
class RiscVJit : public RiscVGen::RiscVCodeBlock, public IRJit {
// TODO: Separate.
class RiscVJit : public RiscVGen::RiscVCodeBlock, public IRNativeJit, public IRNativeBackend {
public:
RiscVJit(MIPSState *mipsState);
~RiscVJit();
@ -65,8 +50,6 @@ public:
protected:
bool CompileTargetBlock(IRBlock *block, int block_num, bool preload) override;
void CompileIRInst(IRInst inst);
private:
void GenerateFixedCode(const JitOptions &jo);
@ -81,48 +64,48 @@ private:
// Note: destroys SCRATCH1.
void FlushAll();
void CompIR_Arith(IRInst inst);
void CompIR_Assign(IRInst inst);
void CompIR_Basic(IRInst inst);
void CompIR_Bits(IRInst inst);
void CompIR_Breakpoint(IRInst inst);
void CompIR_Compare(IRInst inst);
void CompIR_CondAssign(IRInst inst);
void CompIR_CondStore(IRInst inst);
void CompIR_Div(IRInst inst);
void CompIR_Exit(IRInst inst);
void CompIR_ExitIf(IRInst inst);
void CompIR_FArith(IRInst inst);
void CompIR_FAssign(IRInst inst);
void CompIR_FCompare(IRInst inst);
void CompIR_FCondAssign(IRInst inst);
void CompIR_FCvt(IRInst inst);
void CompIR_FLoad(IRInst inst);
void CompIR_FRound(IRInst inst);
void CompIR_FSat(IRInst inst);
void CompIR_FSpecial(IRInst inst);
void CompIR_FStore(IRInst inst);
void CompIR_Generic(IRInst inst);
void CompIR_HiLo(IRInst inst);
void CompIR_Interpret(IRInst inst);
void CompIR_Load(IRInst inst);
void CompIR_LoadShift(IRInst inst);
void CompIR_Logic(IRInst inst);
void CompIR_Mult(IRInst inst);
void CompIR_RoundingMode(IRInst inst);
void CompIR_Shift(IRInst inst);
void CompIR_Store(IRInst inst);
void CompIR_StoreShift(IRInst inst);
void CompIR_System(IRInst inst);
void CompIR_Transfer(IRInst inst);
void CompIR_VecArith(IRInst inst);
void CompIR_VecAssign(IRInst inst);
void CompIR_VecClamp(IRInst inst);
void CompIR_VecHoriz(IRInst inst);
void CompIR_VecLoad(IRInst inst);
void CompIR_VecPack(IRInst inst);
void CompIR_VecStore(IRInst inst);
void CompIR_ValidateAddress(IRInst inst);
void CompIR_Arith(IRInst inst) override;
void CompIR_Assign(IRInst inst) override;
void CompIR_Basic(IRInst inst) override;
void CompIR_Bits(IRInst inst) override;
void CompIR_Breakpoint(IRInst inst) override;
void CompIR_Compare(IRInst inst) override;
void CompIR_CondAssign(IRInst inst) override;
void CompIR_CondStore(IRInst inst) override;
void CompIR_Div(IRInst inst) override;
void CompIR_Exit(IRInst inst) override;
void CompIR_ExitIf(IRInst inst) override;
void CompIR_FArith(IRInst inst) override;
void CompIR_FAssign(IRInst inst) override;
void CompIR_FCompare(IRInst inst) override;
void CompIR_FCondAssign(IRInst inst) override;
void CompIR_FCvt(IRInst inst) override;
void CompIR_FLoad(IRInst inst) override;
void CompIR_FRound(IRInst inst) override;
void CompIR_FSat(IRInst inst) override;
void CompIR_FSpecial(IRInst inst) override;
void CompIR_FStore(IRInst inst) override;
void CompIR_Generic(IRInst inst) override;
void CompIR_HiLo(IRInst inst) override;
void CompIR_Interpret(IRInst inst) override;
void CompIR_Load(IRInst inst) override;
void CompIR_LoadShift(IRInst inst) override;
void CompIR_Logic(IRInst inst) override;
void CompIR_Mult(IRInst inst) override;
void CompIR_RoundingMode(IRInst inst) override;
void CompIR_Shift(IRInst inst) override;
void CompIR_Store(IRInst inst) override;
void CompIR_StoreShift(IRInst inst) override;
void CompIR_System(IRInst inst) override;
void CompIR_Transfer(IRInst inst) override;
void CompIR_VecArith(IRInst inst) override;
void CompIR_VecAssign(IRInst inst) override;
void CompIR_VecClamp(IRInst inst) override;
void CompIR_VecHoriz(IRInst inst) override;
void CompIR_VecLoad(IRInst inst) override;
void CompIR_VecPack(IRInst inst) override;
void CompIR_VecStore(IRInst inst) override;
void CompIR_ValidateAddress(IRInst inst) override;
void SetScratch1ToSrc1Address(IRReg src1);
// Modifies SCRATCH regs.
@ -133,7 +116,7 @@ private:
RiscVRegCache gpr;
RiscVRegCacheFPU fpr;
RiscVBlockCacheDebugInterface debugInterface_;
IRNativeBlockCacheDebugInterface debugInterface_;
const u8 *enterDispatcher_ = nullptr;

2
UWP/CoreUWP/CoreUWP.vcxproj
View file

@ -302,6 +302,7 @@
<ClInclude Include="..\..\Core\MIPS\IR\IRInst.h" />
<ClInclude Include="..\..\Core\MIPS\IR\IRInterpreter.h" />
<ClInclude Include="..\..\Core\MIPS\IR\IRJit.h" />
<ClInclude Include="..\..\Core\MIPS\IR\IRNativeCommon.h" />
<ClInclude Include="..\..\Core\MIPS\IR\IRAnalysis.h" />
<ClInclude Include="..\..\Core\MIPS\IR\IRPassSimplify.h" />
<ClInclude Include="..\..\Core\MIPS\IR\IRRegCache.h" />
@ -562,6 +563,7 @@
<ClCompile Include="..\..\Core\MIPS\IR\IRInst.cpp" />
<ClCompile Include="..\..\Core\MIPS\IR\IRInterpreter.cpp" />
<ClCompile Include="..\..\Core\MIPS\IR\IRJit.cpp" />
<ClCompile Include="..\..\Core\MIPS\IR\IRNativeCommon.cpp" />
<ClCompile Include="..\..\Core\MIPS\IR\IRAnalysis.cpp" />
<ClCompile Include="..\..\Core\MIPS\IR\IRPassSimplify.cpp" />
<ClCompile Include="..\..\Core\MIPS\IR\IRRegCache.cpp" />

6
UWP/CoreUWP/CoreUWP.vcxproj.filters
View file

@ -645,6 +645,9 @@
<ClCompile Include="..\..\Core\MIPS\IR\IRJit.cpp">
<Filter>MIPS\IR</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\IR\IRNativeCommon.cpp">
<Filter>MIPS\IR</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\IR\IRAnalysis.cpp">
<Filter>MIPS\IR</Filter>
</ClCompile>
@ -1670,6 +1673,9 @@
<ClInclude Include="..\..\Core\MIPS\IR\IRJit.h">
<Filter>MIPS\IR</Filter>
</ClInclude>
<ClInclude Include="..\..\Core\MIPS\IR\IRNativeCommon.h">
<Filter>MIPS\IR</Filter>
</ClInclude>
<ClInclude Include="..\..\Core\MIPS\IR\IRAnalysis.h">
<Filter>MIPS\IR</Filter>
</ClInclude>

1
android/jni/Android.mk
View file

@ -400,6 +400,7 @@ EXEC_AND_LIB_FILES := \
$(SRC)/Core/MIPS/IR/IRCompVFPU.cpp \
$(SRC)/Core/MIPS/IR/IRInst.cpp \
$(SRC)/Core/MIPS/IR/IRInterpreter.cpp \
$(SRC)/Core/MIPS/IR/IRNativeCommon.cpp \
$(SRC)/Core/MIPS/IR/IRPassSimplify.cpp \
$(SRC)/Core/MIPS/IR/IRRegCache.cpp \
$(SRC)/GPU/Math3D.cpp \

3
libretro/Makefile.common
View file

@ -677,9 +677,10 @@ SOURCES_CXX += \
$(COREDIR)/MIPS/IR/IRCompFPU.cpp \
$(COREDIR)/MIPS/IR/IRCompLoadStore.cpp \
$(COREDIR)/MIPS/IR/IRCompVFPU.cpp \
$(COREDIR)/MIPS/IR/IRInst.cpp \
$(COREDIR)/MIPS/IR/IRInterpreter.cpp \
$(COREDIR)/MIPS/IR/IRJit.cpp \
$(COREDIR)/MIPS/IR/IRInst.cpp \
$(COREDIR)/MIPS/IR/IRNativeCommon.cpp \
$(COREDIR)/MIPS/IR/IRPassSimplify.cpp \
$(COREDIR)/MIPS/IR/IRRegCache.cpp \
$(COREDIR)/MIPS/IR/IRFrontend.cpp \