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riscv: Remove FMul safety check.
Let's just see if everything's right, this bloats multiplies a lot. Doesn't seem to impact perf a lot, though.
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1 changed files with 3 additions and 35 deletions
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@ -50,41 +50,9 @@ void RiscVJitBackend::CompIR_FArith(IRInst inst) {
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case IROp::FMul:
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fpr.MapDirtyInIn(inst.dest, inst.src1, inst.src2);
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// TODO: If FMUL consistently produces NAN across chip vendors, we can skip this.
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// Luckily this does match the RISC-V canonical NAN.
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if (inst.src1 != inst.src2) {
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// These will output 0x80/0x01 if infinity, 0x10/0x80 if zero.
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// We need to check if one is infinity and the other zero.
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// First, try inf * zero.
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FCLASS(32, SCRATCH1, fpr.R(inst.src1));
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FCLASS(32, SCRATCH2, fpr.R(inst.src2));
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ANDI(R_RA, SCRATCH1, 0x81);
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FixupBranch lhsNotInf = BEQ(R_RA, R_ZERO);
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ANDI(R_RA, SCRATCH2, 0x18);
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FixupBranch infZero = BNE(R_RA, R_ZERO);
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// Okay, what about the other order?
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SetJumpTarget(lhsNotInf);
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ANDI(R_RA, SCRATCH1, 0x18);
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FixupBranch lhsNotZero = BEQ(R_RA, R_ZERO);
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ANDI(R_RA, SCRATCH2, 0x81);
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FixupBranch zeroInf = BNE(R_RA, R_ZERO);
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// Nope, all good.
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SetJumpTarget(lhsNotZero);
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FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
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FixupBranch skip = J();
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SetJumpTarget(infZero);
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SetJumpTarget(zeroInf);
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LI(SCRATCH1, 0x7FC00000);
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FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
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SetJumpTarget(skip);
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} else {
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FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
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}
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// We'll assume everyone will make it such that 0 * infinity = NAN properly.
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// See blame on this comment if that proves untrue.
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FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
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break;
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case IROp::FDiv:
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