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Merge pull request #17899 from unknownbrackets/riscv-minor

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Minor RISC-V cleanups, frame profiler fix
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Unknown W. Brackets 2023-08-13 11:19:42 -07:00 • committed by GitHub
commit f03cd0b2ad
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4 changed files with 11 additions and 41 deletions
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38
Core/MIPS/RiscV/RiscVCompFPU.cpp
View file

@ -50,41 +50,9 @@ void RiscVJitBackend::CompIR_FArith(IRInst inst) {
case IROp::FMul:
fpr.MapDirtyInIn(inst.dest, inst.src1, inst.src2);
// TODO: If FMUL consistently produces NAN across chip vendors, we can skip this.
// Luckily this does match the RISC-V canonical NAN.
if (inst.src1 != inst.src2) {
// These will output 0x80/0x01 if infinity, 0x10/0x80 if zero.
// We need to check if one is infinity and the other zero.
// First, try inf * zero.
FCLASS(32, SCRATCH1, fpr.R(inst.src1));
FCLASS(32, SCRATCH2, fpr.R(inst.src2));
ANDI(R_RA, SCRATCH1, 0x81);
FixupBranch lhsNotInf = BEQ(R_RA, R_ZERO);
ANDI(R_RA, SCRATCH2, 0x18);
FixupBranch infZero = BNE(R_RA, R_ZERO);
// Okay, what about the other order?
SetJumpTarget(lhsNotInf);
ANDI(R_RA, SCRATCH1, 0x18);
FixupBranch lhsNotZero = BEQ(R_RA, R_ZERO);
ANDI(R_RA, SCRATCH2, 0x81);
FixupBranch zeroInf = BNE(R_RA, R_ZERO);
// Nope, all good.
SetJumpTarget(lhsNotZero);
FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
FixupBranch skip = J();
SetJumpTarget(infZero);
SetJumpTarget(zeroInf);
LI(SCRATCH1, 0x7FC00000);
FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
SetJumpTarget(skip);
} else {
FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
}
// We'll assume everyone will make it such that 0 * infinity = NAN properly.
// See blame on this comment if that proves untrue.
FMUL(32, fpr.R(inst.dest), fpr.R(inst.src1), fpr.R(inst.src2));
break;
case IROp::FDiv:

7
Core/MIPS/RiscV/RiscVCompLoadStore.cpp
View file

@ -80,11 +80,8 @@ void RiscVJitBackend::CompIR_Load(IRInst inst) {
SetScratch1ToSrc1Address(inst.src1);
addrReg = SCRATCH1;
}
// If they're the same, MapReg may subtract MEMBASEREG, so just mark dirty.
if (inst.dest == inst.src1)
gpr.MarkDirty(gpr.R(inst.dest), true);
else
gpr.MapReg(inst.dest, MIPSMap::NOINIT | MIPSMap::MARK_NORM32);
// With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1.
gpr.MapReg(inst.dest, MIPSMap::NOINIT | MIPSMap::MARK_NORM32);
gpr.ReleaseSpillLock(inst.dest, inst.src1);
s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);

5
GPU/Common/TextureDecoder.cpp
View file

@ -243,8 +243,13 @@ static u32 QuickTexHashNonSSE(const void *checkp, u32 size) {
if (((intptr_t)checkp & 0xf) == 0 && (size & 0x3f) == 0) {
static const u16 cursor2_initial[8] = {0xc00bU, 0x9bd9U, 0x4b73U, 0xb651U, 0x4d9bU, 0x4309U, 0x0083U, 0x0001U};
union u32x4_u16x8 {
#if defined(__GNUC__)
uint32_t x32 __attribute__((vector_size(16)));
uint16_t x16 __attribute__((vector_size(16)));
#else
u32 x32[4];
u16 x16[8];
#endif
};
u32x4_u16x8 cursor{};
u32x4_u16x8 cursor2;

2
UI/EmuScreen.cpp
View file

@ -1548,7 +1548,7 @@ void EmuScreen::renderUI() {
}
#ifdef USE_PROFILER
if (g_Config.bShowFrameProfiler && !invalid_) {
if ((DebugOverlay)g_Config.iDebugOverlay == DebugOverlay::FRAME_PROFILE && !invalid_) {
DrawProfile(*ctx);
}
#endif