mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
irjit: Move more to IRNativeBackend, split.
This commit is contained in:
Unknown W. Brackets
parent
691799a0ca
commit
93e3d35f5d
13 changed files with 365 additions and 236 deletions
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@ -32,7 +32,7 @@ public:
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virtual const u8 *GetCodePtr() const = 0;
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u8 *GetBasePtr() {
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u8 *GetBasePtr() const {
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return region;
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}
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@ -124,6 +124,13 @@ public:
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return nullptr;
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}
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}
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const IRBlock *GetBlock(int i) const {
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if (i >= 0 && i < (int)blocks_.size()) {
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return &blocks_[i];
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} else {
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return nullptr;
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}
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}
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int FindPreloadBlock(u32 em_address);
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int FindByCookie(int cookie);
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@ -180,7 +187,7 @@ public:
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void UnlinkBlock(u8 *checkedEntry, u32 originalAddress) override;
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protected:
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virtual bool CompileBlock(u32 em_address, std::vector<IRInst> &instructions, u32 &mipsBytes, bool preload);
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bool CompileBlock(u32 em_address, std::vector<IRInst> &instructions, u32 &mipsBytes, bool preload);
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virtual bool CompileTargetBlock(IRBlock *block, int block_num, bool preload) { return true; }
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JitOptions jo;
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@ -16,12 +16,87 @@
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Common/Profiler/Profiler.h"
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#include "Common/StringUtils.h"
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#include "Common/TimeUtil.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/IR/IRNativeCommon.h"
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using namespace MIPSComp;
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namespace MIPSComp {
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// Compile time flag to enable debug stats for not compiled ops.
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static constexpr bool enableDebugStats = false;
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// Used only for debugging when enableDebug is true above.
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static std::map<uint8_t, int> debugSeenNotCompiledIR;
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static std::map<const char *, int> debugSeenNotCompiled;
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static double lastDebugStatsLog = 0.0;
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static void LogDebugStats() {
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if (!enableDebugStats)
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return;
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double now = time_now_d();
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if (now < lastDebugStatsLog + 1.0)
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return;
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lastDebugStatsLog = now;
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int worstIROp = -1;
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int worstIRVal = 0;
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for (auto it : debugSeenNotCompiledIR) {
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if (it.second > worstIRVal) {
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worstIRVal = it.second;
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worstIROp = it.first;
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}
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}
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debugSeenNotCompiledIR.clear();
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const char *worstName = nullptr;
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int worstVal = 0;
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for (auto it : debugSeenNotCompiled) {
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if (it.second > worstVal) {
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worstVal = it.second;
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worstName = it.first;
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}
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}
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debugSeenNotCompiled.clear();
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if (worstIROp != -1)
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WARN_LOG(JIT, "Most not compiled IR op: %s (%d)", GetIRMeta((IROp)worstIROp)->name, worstIRVal);
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if (worstName != nullptr)
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WARN_LOG(JIT, "Most not compiled op: %s (%d)", worstName, worstVal);
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}
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bool IRNativeBackend::DebugStatsEnabled() const {
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return enableDebugStats;
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}
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void IRNativeBackend::NotifyMIPSInterpret(const char *name) {
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_assert_(enableDebugStats);
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debugSeenNotCompiled[name]++;
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}
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void IRNativeBackend::DoMIPSInst(uint32_t value) {
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MIPSOpcode op;
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memcpy(&op, &value, sizeof(op));
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if constexpr (enableDebugStats)
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debugSeenNotCompiled[MIPSGetName(op)]++;
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MIPSInterpret(op);
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}
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uint32_t IRNativeBackend::DoIRInst(uint64_t value) {
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IRInst inst;
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memcpy(&inst, &value, sizeof(inst));
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if constexpr (enableDebugStats)
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debugSeenNotCompiledIR[(uint8_t)inst.op]++;
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return IRInterpret(currentMIPS, &inst, 1);
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}
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void IRNativeBackend::CompileIRInst(IRInst inst) {
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switch (inst.op) {
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case IROp::Nop:
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@ -312,10 +387,127 @@ void IRNativeBackend::CompileIRInst(IRInst inst) {
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}
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}
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IRNativeJit::IRNativeJit(MIPSState *mipsState)
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: IRJit(mipsState), debugInterface_(blocks_) {}
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void IRNativeJit::Init(IRNativeBackend &backend) {
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backend_ = &backend;
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debugInterface_.Init(&backend_->CodeBlock());
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backend_->GenerateFixedCode();
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// Wanted this to be a reference, but vtbls get in the way. Shouldn't change.
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hooks_ = backend.GetNativeHooks();
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}
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bool IRNativeJit::CompileTargetBlock(IRBlock *block, int block_num, bool preload) {
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return backend_->CompileBlock(block, block_num, preload);
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}
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void IRNativeJit::RunLoopUntil(u64 globalticks) {
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if constexpr (enableDebugStats) {
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LogDebugStats();
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}
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PROFILE_THIS_SCOPE("jit");
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hooks_.enterDispatcher();
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}
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void IRNativeJit::ClearCache() {
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IRJit::ClearCache();
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backend_->ClearAllBlocks();
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}
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bool IRNativeJit::DescribeCodePtr(const u8 *ptr, std::string &name) {
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if (ptr != nullptr && backend_->DescribeCodePtr(ptr, name))
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return true;
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int offset = backend_->OffsetFromCodePtr(ptr);
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if (offset == -1)
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return false;
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int block_num = -1;
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for (int i = 0; i < blocks_.GetNumBlocks(); ++i) {
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const auto &b = blocks_.GetBlock(i);
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// We allocate linearly.
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if (b->GetTargetOffset() <= offset)
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block_num = i;
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if (b->GetTargetOffset() > offset)
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break;
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}
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if (block_num == -1) {
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name = "(unknown or deleted block)";
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return true;
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}
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const IRBlock *block = blocks_.GetBlock(block_num);
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if (block) {
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u32 start = 0, size = 0;
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block->GetRange(start, size);
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name = StringFromFormat("(block %d at %08x)", block_num, start);
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return true;
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}
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return false;
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}
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bool IRNativeJit::CodeInRange(const u8 *ptr) const {
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return backend_->CodeInRange(ptr);
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}
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bool IRNativeJit::IsAtDispatchFetch(const u8 *ptr) const {
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return ptr == backend_->GetNativeHooks().dispatchFetch;
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}
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const u8 *IRNativeJit::GetDispatcher() const {
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return backend_->GetNativeHooks().dispatcher;
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}
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const u8 *IRNativeJit::GetCrashHandler() const {
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return backend_->GetNativeHooks().crashHandler;
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}
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JitBlockCacheDebugInterface *IRNativeJit::GetBlockCacheDebugInterface() {
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return &debugInterface_;
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}
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bool IRNativeBackend::CodeInRange(const u8 *ptr) const {
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return CodeBlock().IsInSpace(ptr);
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}
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bool IRNativeBackend::DescribeCodePtr(const u8 *ptr, std::string &name) const {
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if (!CodeBlock().IsInSpace(ptr))
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return false;
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// Used in disassembly viewer.
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if (ptr == (const uint8_t *)hooks_.enterDispatcher) {
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name = "enterDispatcher";
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} else if (ptr == hooks_.dispatcher) {
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name = "dispatcher";
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} else if (ptr == hooks_.dispatchFetch) {
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name = "dispatchFetch";
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} else if (ptr == hooks_.crashHandler) {
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name = "crashHandler";
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} else {
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return false;
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}
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return true;
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}
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int IRNativeBackend::OffsetFromCodePtr(const u8 *ptr) {
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auto &codeBlock = CodeBlock();
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if (!codeBlock.IsInSpace(ptr))
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return -1;
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return (int)codeBlock.GetOffset(ptr);
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}
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} // namespace MIPSComp
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IRNativeBlockCacheDebugInterface::IRNativeBlockCacheDebugInterface(IRBlockCache &irBlocks, CodeBlockCommon &codeBlock)
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: irBlocks_(irBlocks), codeBlock_(codeBlock) {}
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IRNativeBlockCacheDebugInterface::IRNativeBlockCacheDebugInterface(const IRBlockCache &irBlocks)
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: irBlocks_(irBlocks) {}
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void IRNativeBlockCacheDebugInterface::Init(const CodeBlockCommon *codeBlock) {
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codeBlock_ = codeBlock;
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}
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int IRNativeBlockCacheDebugInterface::GetNumBlocks() const {
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return irBlocks_.GetNumBlocks();
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@ -331,7 +523,7 @@ void IRNativeBlockCacheDebugInterface::GetBlockCodeRange(int blockNum, int *star
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// We assume linear allocation. Maybe a bit dangerous, should always be right.
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if (blockNum + 1 >= GetNumBlocks()) {
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// Last block, get from current code pointer.
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endOffset = (int)codeBlock_.GetOffset(codeBlock_.GetCodePtr());
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endOffset = (int)codeBlock_->GetOffset(codeBlock_->GetCodePtr());
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} else {
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endOffset = irBlocks_.GetBlock(blockNum + 1)->GetTargetOffset();
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_assert_msg_(endOffset >= blockOffset, "Next block not sequential, block=%d/%08x, next=%d/%08x", blockNum, blockOffset, blockNum + 1, endOffset);
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@ -348,7 +540,7 @@ JitBlockDebugInfo IRNativeBlockCacheDebugInterface::GetBlockDebugInfo(int blockN
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GetBlockCodeRange(blockNum, &blockOffset, &codeSize);
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// TODO: Normal entry?
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const u8 *blockStart = codeBlock_.GetBasePtr() + blockOffset;
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const u8 *blockStart = codeBlock_->GetBasePtr() + blockOffset;
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#if PPSSPP_ARCH(ARM)
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debugInfo.targetDisasm = DisassembleArm2(blockStart, codeSize);
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#elif PPSSPP_ARCH(ARM64)
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@ -20,7 +20,8 @@
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class IRNativeBlockCacheDebugInterface : public JitBlockCacheDebugInterface {
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public:
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IRNativeBlockCacheDebugInterface(MIPSComp::IRBlockCache &irBlocks, CodeBlockCommon &codeBlock);
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IRNativeBlockCacheDebugInterface(const MIPSComp::IRBlockCache &irBlocks);
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void Init(const CodeBlockCommon *codeBlock);
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int GetNumBlocks() const;
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int GetBlockNumberFromStartAddress(u32 em_address, bool realBlocksOnly = true) const;
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JitBlockDebugInfo GetBlockDebugInfo(int blockNum) const;
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@ -29,18 +30,42 @@ public:
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private:
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void GetBlockCodeRange(int blockNum, int *startOffset, int *size) const;
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MIPSComp::IRBlockCache &irBlocks_;
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CodeBlockCommon &codeBlock_;
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const MIPSComp::IRBlockCache &irBlocks_;
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const CodeBlockCommon *codeBlock_ = nullptr;
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};
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namespace MIPSComp {
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typedef void (*IRNativeFuncNoArg)();
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struct IRNativeHooks {
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IRNativeFuncNoArg enterDispatcher = nullptr;
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const uint8_t *dispatcher = nullptr;
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const uint8_t *dispatchFetch = nullptr;
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const uint8_t *crashHandler = nullptr;
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};
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class IRNativeBackend {
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public:
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virtual ~IRNativeBackend() {}
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void CompileIRInst(IRInst inst);
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virtual bool DescribeCodePtr(const u8 *ptr, std::string &name) const;
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bool CodeInRange(const u8 *ptr) const;
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int OffsetFromCodePtr(const u8 *ptr);
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virtual void GenerateFixedCode() = 0;
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virtual bool CompileBlock(IRBlock *block, int block_num, bool preload) = 0;
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virtual void ClearAllBlocks() = 0;
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const IRNativeHooks &GetNativeHooks() const {
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return hooks_;
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}
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virtual const CodeBlockCommon &CodeBlock() const = 0;
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protected:
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virtual void CompIR_Arith(IRInst inst) = 0;
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virtual void CompIR_Assign(IRInst inst) = 0;
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@ -84,11 +109,46 @@ protected:
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virtual void CompIR_VecPack(IRInst inst) = 0;
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virtual void CompIR_VecStore(IRInst inst) = 0;
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virtual void CompIR_ValidateAddress(IRInst inst) = 0;
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// Returns true when debugging statistics should be compiled in.
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bool DebugStatsEnabled() const;
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// Callback (compile when DebugStatsEnabled()) to log a base interpreter hit.
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// Call the func returned by MIPSGetInterpretFunc(op) directly for interpret.
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static void NotifyMIPSInterpret(const char *name);
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// Callback to log AND perform a base interpreter op. Alternative to NotifyMIPSInterpret().
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static void DoMIPSInst(uint32_t op);
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// Callback to log AND perform an IR interpreter inst. Returns 0 or a PC to jump to.
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static uint32_t DoIRInst(uint64_t inst);
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IRNativeHooks hooks_;
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};
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class IRNativeJit : public IRJit {
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public:
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IRNativeJit(MIPSState *mipsState) : IRJit(mipsState) {}
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IRNativeJit(MIPSState *mipsState);
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void RunLoopUntil(u64 globalticks) override;
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void ClearCache() override;
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bool DescribeCodePtr(const u8 *ptr, std::string &name) override;
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bool CodeInRange(const u8 *ptr) const override;
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bool IsAtDispatchFetch(const u8 *ptr) const override;
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const u8 *GetDispatcher() const override;
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const u8 *GetCrashHandler() const override;
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JitBlockCacheDebugInterface *GetBlockCacheDebugInterface() override;
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protected:
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void Init(IRNativeBackend &backend);
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bool CompileTargetBlock(IRBlock *block, int block_num, bool preload) override;
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IRNativeBackend *backend_ = nullptr;
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IRNativeHooks hooks_;
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IRNativeBlockCacheDebugInterface debugInterface_;
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};
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} // namespace MIPSComp
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@ -44,17 +44,7 @@ static void ShowPC(u32 downcount, void *membase, void *jitbase) {
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count++;
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}
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static void ShowBlockError(int type) {
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if (type == 1) {
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ERROR_LOG(JIT, "[%08x] ShowBlockError: block num was out of range in emuhack", currentMIPS->pc);
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} else if (type == 2) {
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ERROR_LOG(JIT, "[%08x] ShowBlockError: block num pointed to null jitblock", currentMIPS->pc);
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} else {
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ERROR_LOG(JIT, "[%08x] ShowBlockError: invalid error type", currentMIPS->pc);
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}
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}
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void RiscVJit::GenerateFixedCode(const JitOptions &jo) {
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void RiscVJitBackend::GenerateFixedCode() {
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BeginWrite(GetMemoryProtectPageSize());
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const u8 *start = AlignCodePage();
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@ -104,7 +94,7 @@ void RiscVJit::GenerateFixedCode(const JitOptions &jo) {
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RET();
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}
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enterDispatcher_ = AlignCode16();
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hooks_.enterDispatcher = (IRNativeFuncNoArg)AlignCode16();
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// Start by saving some regs on the stack. There are 12 GPs and 12 FPs we want.
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// Note: we leave R_SP as, well, SP, so it doesn't need to be saved.
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@ -157,7 +147,7 @@ void RiscVJit::GenerateFixedCode(const JitOptions &jo) {
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dispatcherPCInSCRATCH1_ = GetCodePtr();
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MovToPC(SCRATCH1);
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dispatcher_ = GetCodePtr();
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hooks_.dispatcher = GetCodePtr();
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FixupBranch bail = BLT(DOWNCOUNTREG, R_ZERO);
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SetJumpTarget(skipToRealDispatch);
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@ -177,7 +167,7 @@ void RiscVJit::GenerateFixedCode(const JitOptions &jo) {
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AND(SCRATCH1, SCRATCH1, SCRATCH2);
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#endif
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ADD(SCRATCH1, SCRATCH1, MEMBASEREG);
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dispatcherFetch_ = GetCodePtr();
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hooks_.dispatchFetch = GetCodePtr();
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LWU(SCRATCH1, SCRATCH1, 0);
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SRLI(SCRATCH2, SCRATCH1, 24);
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// We're in other words comparing to the top 8 bits of MIPS_EMUHACK_OPCODE by subtracting.
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@ -224,7 +214,7 @@ void RiscVJit::GenerateFixedCode(const JitOptions &jo) {
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RET();
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crashHandler_ = GetCodePtr();
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hooks_.crashHandler = GetCodePtr();
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LI(SCRATCH1, &coreState, SCRATCH2);
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LI(SCRATCH2, CORE_RUNTIME_ERROR);
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SW(SCRATCH2, SCRATCH1, 0);
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@ -35,7 +35,7 @@ namespace MIPSComp {
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using namespace RiscVGen;
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using namespace RiscVJitConstants;
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void RiscVJit::CompIR_Arith(IRInst inst) {
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void RiscVJitBackend::CompIR_Arith(IRInst inst) {
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CONDITIONAL_DISABLE;
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bool allowPtrMath = true;
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@ -96,7 +96,7 @@ void RiscVJit::CompIR_Arith(IRInst inst) {
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}
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}
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void RiscVJit::CompIR_Logic(IRInst inst) {
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void RiscVJitBackend::CompIR_Logic(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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@ -187,7 +187,7 @@ void RiscVJit::CompIR_Logic(IRInst inst) {
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}
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}
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void RiscVJit::CompIR_Assign(IRInst inst) {
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void RiscVJitBackend::CompIR_Assign(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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@ -227,7 +227,7 @@ void RiscVJit::CompIR_Assign(IRInst inst) {
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}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Bits(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Bits(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -269,7 +269,7 @@ void RiscVJit::CompIR_Bits(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Shift(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Shift(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -367,7 +367,7 @@ void RiscVJit::CompIR_Shift(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Compare(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Compare(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg lhs = INVALID_REG;
|
||||
|
|
@ -445,7 +445,7 @@ void RiscVJit::CompIR_Compare(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_CondAssign(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_CondAssign(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg lhs = INVALID_REG;
|
||||
|
|
@ -519,7 +519,7 @@ void RiscVJit::CompIR_CondAssign(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_HiLo(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_HiLo(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -553,7 +553,7 @@ void RiscVJit::CompIR_HiLo(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Mult(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Mult(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
auto makeArgsUnsigned = [&](RiscVReg *lhs, RiscVReg *rhs) {
|
||||
|
|
@ -652,7 +652,7 @@ void RiscVJit::CompIR_Mult(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Div(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Div(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg numReg, denomReg;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ namespace MIPSComp {
|
|||
using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
void RiscVJit::CompIR_Exit(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Exit(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg exitReg = INVALID_REG;
|
||||
|
|
@ -64,7 +64,7 @@ void RiscVJit::CompIR_Exit(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_ExitIf(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_ExitIf(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg lhs = INVALID_REG;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ namespace MIPSComp {
|
|||
using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
void RiscVJit::CompIR_FArith(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FArith(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -108,7 +108,7 @@ void RiscVJit::CompIR_FArith(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FCondAssign(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FCondAssign(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
if (inst.op != IROp::FMin && inst.op != IROp::FMax)
|
||||
INVALIDOP;
|
||||
|
|
@ -174,7 +174,7 @@ void RiscVJit::CompIR_FCondAssign(IRInst inst) {
|
|||
SetJumpTarget(finish);
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FAssign(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FAssign(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -220,7 +220,7 @@ void RiscVJit::CompIR_FAssign(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FRound(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FRound(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
// TODO: If this is followed by a GPR transfer, might want to combine.
|
||||
|
|
@ -251,7 +251,7 @@ void RiscVJit::CompIR_FRound(IRInst inst) {
|
|||
FMV(FMv::W, FMv::X, fpr.R(inst.dest), SCRATCH1);
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FCvt(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FCvt(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -274,7 +274,7 @@ void RiscVJit::CompIR_FCvt(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FSat(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FSat(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg tempReg = INVALID_REG;
|
||||
|
|
@ -334,7 +334,7 @@ void RiscVJit::CompIR_FSat(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FCompare(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FCompare(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
constexpr IRRegIndex IRREG_VFPUL_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC;
|
||||
|
|
@ -548,7 +548,7 @@ void RiscVJit::CompIR_FCompare(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_RoundingMode(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_RoundingMode(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -570,7 +570,7 @@ void RiscVJit::CompIR_RoundingMode(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FSpecial(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FSpecial(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
#ifdef __riscv_float_abi_soft
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ namespace MIPSComp {
|
|||
using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
void RiscVJit::SetScratch1ToSrc1Address(IRReg src1) {
|
||||
void RiscVJitBackend::SetScratch1ToSrc1Address(IRReg src1) {
|
||||
gpr.MapReg(src1);
|
||||
#ifdef MASKED_PSP_MEMORY
|
||||
SLLIW(SCRATCH1, gpr.R(src1), 2);
|
||||
|
|
@ -53,7 +53,7 @@ void RiscVJit::SetScratch1ToSrc1Address(IRReg src1) {
|
|||
#endif
|
||||
}
|
||||
|
||||
int32_t RiscVJit::AdjustForAddressOffset(RiscVGen::RiscVReg *reg, int32_t constant, int32_t range) {
|
||||
int32_t RiscVJitBackend::AdjustForAddressOffset(RiscVGen::RiscVReg *reg, int32_t constant, int32_t range) {
|
||||
if (constant < -2048 || constant + range > 2047) {
|
||||
LI(SCRATCH2, constant);
|
||||
ADD(SCRATCH1, *reg, SCRATCH2);
|
||||
|
|
@ -63,7 +63,7 @@ int32_t RiscVJit::AdjustForAddressOffset(RiscVGen::RiscVReg *reg, int32_t consta
|
|||
return constant;
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Load(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Load(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
gpr.SpillLock(inst.dest, inst.src1);
|
||||
|
|
@ -124,7 +124,7 @@ void RiscVJit::CompIR_Load(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_LoadShift(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_LoadShift(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -140,7 +140,7 @@ void RiscVJit::CompIR_LoadShift(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FLoad(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FLoad(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg addrReg = INVALID_REG;
|
||||
|
|
@ -173,7 +173,7 @@ void RiscVJit::CompIR_FLoad(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_VecLoad(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecLoad(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg addrReg = INVALID_REG;
|
||||
|
|
@ -210,7 +210,7 @@ void RiscVJit::CompIR_VecLoad(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Store(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Store(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
gpr.SpillLock(inst.src3, inst.src1);
|
||||
|
|
@ -255,7 +255,7 @@ void RiscVJit::CompIR_Store(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_CondStore(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_CondStore(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
if (inst.op != IROp::Store32Conditional)
|
||||
INVALIDOP;
|
||||
|
|
@ -297,7 +297,7 @@ void RiscVJit::CompIR_CondStore(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_StoreShift(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_StoreShift(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -313,7 +313,7 @@ void RiscVJit::CompIR_StoreShift(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_FStore(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_FStore(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg addrReg = INVALID_REG;
|
||||
|
|
@ -346,7 +346,7 @@ void RiscVJit::CompIR_FStore(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_VecStore(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecStore(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
RiscVReg addrReg = INVALID_REG;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ namespace MIPSComp {
|
|||
using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
void RiscVJit::CompIR_Basic(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Basic(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -85,7 +85,7 @@ void RiscVJit::CompIR_Basic(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Transfer(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Transfer(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -177,7 +177,7 @@ void RiscVJit::CompIR_Transfer(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_System(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_System(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -236,7 +236,7 @@ void RiscVJit::CompIR_System(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Breakpoint(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Breakpoint(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -251,7 +251,7 @@ void RiscVJit::CompIR_Breakpoint(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_ValidateAddress(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_ValidateAddress(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ namespace MIPSComp {
|
|||
using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
void RiscVJit::CompIR_VecAssign(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecAssign(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -129,7 +129,7 @@ void RiscVJit::CompIR_VecAssign(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_VecArith(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecArith(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -184,7 +184,7 @@ void RiscVJit::CompIR_VecArith(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_VecHoriz(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecHoriz(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -230,7 +230,7 @@ void RiscVJit::CompIR_VecHoriz(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_VecPack(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecPack(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
@ -266,7 +266,7 @@ void RiscVJit::CompIR_VecPack(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_VecClamp(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_VecClamp(IRInst inst) {
|
||||
CONDITIONAL_DISABLE;
|
||||
|
||||
switch (inst.op) {
|
||||
|
|
|
|||
|
|
@ -15,62 +15,18 @@
|
|||
// Official git repository and contact information can be found at
|
||||
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
|
||||
|
||||
#include "Common/StringUtils.h"
|
||||
#include "Common/TimeUtil.h"
|
||||
#include "Core/MemMap.h"
|
||||
#include "Core/MIPS/MIPSTables.h"
|
||||
#include "Core/MIPS/RiscV/RiscVJit.h"
|
||||
#include "Core/MIPS/RiscV/RiscVRegCache.h"
|
||||
#include "Common/Profiler/Profiler.h"
|
||||
|
||||
namespace MIPSComp {
|
||||
|
||||
using namespace RiscVGen;
|
||||
using namespace RiscVJitConstants;
|
||||
|
||||
static constexpr bool enableDebug = false;
|
||||
|
||||
static std::map<uint8_t, int> debugSeenNotCompiledIR;
|
||||
static std::map<const char *, int> debugSeenNotCompiled;
|
||||
double lastDebugLog = 0.0;
|
||||
|
||||
static void LogDebugNotCompiled() {
|
||||
if (!enableDebug)
|
||||
return;
|
||||
|
||||
double now = time_now_d();
|
||||
if (now < lastDebugLog + 1.0)
|
||||
return;
|
||||
lastDebugLog = now;
|
||||
|
||||
int worstIROp = -1;
|
||||
int worstIRVal = 0;
|
||||
for (auto it : debugSeenNotCompiledIR) {
|
||||
if (it.second > worstIRVal) {
|
||||
worstIRVal = it.second;
|
||||
worstIROp = it.first;
|
||||
}
|
||||
}
|
||||
debugSeenNotCompiledIR.clear();
|
||||
|
||||
const char *worstName = nullptr;
|
||||
int worstVal = 0;
|
||||
for (auto it : debugSeenNotCompiled) {
|
||||
if (it.second > worstVal) {
|
||||
worstVal = it.second;
|
||||
worstName = it.first;
|
||||
}
|
||||
}
|
||||
debugSeenNotCompiled.clear();
|
||||
|
||||
if (worstIROp != -1)
|
||||
WARN_LOG(JIT, "Most not compiled IR op: %s (%d)", GetIRMeta((IROp)worstIROp)->name, worstIRVal);
|
||||
if (worstName != nullptr)
|
||||
WARN_LOG(JIT, "Most not compiled op: %s (%d)", worstName, worstVal);
|
||||
}
|
||||
|
||||
RiscVJit::RiscVJit(MIPSState *mipsState)
|
||||
: IRNativeJit(mipsState), gpr(mipsState, &jo), fpr(mipsState, &jo), debugInterface_(blocks_, *this) {
|
||||
RiscVJitBackend::RiscVJitBackend(MIPSState *mipsState, JitOptions &jitopt)
|
||||
: mips_(mipsState), jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) {
|
||||
// Automatically disable incompatible options.
|
||||
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
|
||||
jo.enablePointerify = false;
|
||||
|
|
@ -83,31 +39,16 @@ RiscVJit::RiscVJit(MIPSState *mipsState)
|
|||
|
||||
gpr.Init(this);
|
||||
fpr.Init(this);
|
||||
|
||||
GenerateFixedCode(jo);
|
||||
}
|
||||
|
||||
RiscVJit::~RiscVJit() {
|
||||
}
|
||||
|
||||
void RiscVJit::RunLoopUntil(u64 globalticks) {
|
||||
if constexpr (enableDebug) {
|
||||
LogDebugNotCompiled();
|
||||
}
|
||||
|
||||
PROFILE_THIS_SCOPE("jit");
|
||||
((void (*)())enterDispatcher_)();
|
||||
}
|
||||
|
||||
JitBlockCacheDebugInterface *MIPSComp::RiscVJit::GetBlockCacheDebugInterface() {
|
||||
return &debugInterface_;
|
||||
RiscVJitBackend::~RiscVJitBackend() {
|
||||
}
|
||||
|
||||
static void NoBlockExits() {
|
||||
_assert_msg_(false, "Never exited block, invalid IR?");
|
||||
}
|
||||
|
||||
bool RiscVJit::CompileTargetBlock(IRBlock *block, int block_num, bool preload) {
|
||||
bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) {
|
||||
if (GetSpaceLeft() < 0x800)
|
||||
return false;
|
||||
|
||||
|
|
@ -138,9 +79,10 @@ bool RiscVJit::CompileTargetBlock(IRBlock *block, int block_num, bool preload) {
|
|||
}
|
||||
|
||||
// We should've written an exit above. If we didn't, bad things will happen.
|
||||
if (enableDebug) {
|
||||
// Only check if debug stats are enabled - needlessly wastes jit space.
|
||||
if (DebugStatsEnabled()) {
|
||||
QuickCallFunction(&NoBlockExits);
|
||||
QuickJ(R_RA, crashHandler_);
|
||||
QuickJ(R_RA, hooks_.crashHandler);
|
||||
}
|
||||
|
||||
FlushIcache();
|
||||
|
|
@ -148,17 +90,7 @@ bool RiscVJit::CompileTargetBlock(IRBlock *block, int block_num, bool preload) {
|
|||
return true;
|
||||
}
|
||||
|
||||
static u32 DoIRInst(uint64_t value) {
|
||||
IRInst inst;
|
||||
memcpy(&inst, &value, sizeof(inst));
|
||||
|
||||
if constexpr (enableDebug)
|
||||
debugSeenNotCompiledIR[(uint8_t)inst.op]++;
|
||||
|
||||
return IRInterpret(currentMIPS, &inst, 1);
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Generic(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Generic(IRInst inst) {
|
||||
// If we got here, we're going the slow way.
|
||||
uint64_t value;
|
||||
memcpy(&value, &inst, sizeof(inst));
|
||||
|
|
@ -183,36 +115,29 @@ void RiscVJit::CompIR_Generic(IRInst inst) {
|
|||
}
|
||||
}
|
||||
|
||||
static void DebugInterpretHit(const char *name) {
|
||||
if (enableDebug)
|
||||
debugSeenNotCompiled[name]++;
|
||||
}
|
||||
|
||||
void RiscVJit::CompIR_Interpret(IRInst inst) {
|
||||
void RiscVJitBackend::CompIR_Interpret(IRInst inst) {
|
||||
MIPSOpcode op(inst.constant);
|
||||
|
||||
// IR protects us against this being a branching instruction (well, hopefully.)
|
||||
FlushAll();
|
||||
SaveStaticRegisters();
|
||||
if (enableDebug) {
|
||||
if (DebugStatsEnabled()) {
|
||||
LI(X10, MIPSGetName(op));
|
||||
QuickCallFunction(&DebugInterpretHit);
|
||||
QuickCallFunction(&NotifyMIPSInterpret);
|
||||
}
|
||||
LI(X10, (int32_t)inst.constant);
|
||||
QuickCallFunction((const u8 *)MIPSGetInterpretFunc(op));
|
||||
LoadStaticRegisters();
|
||||
}
|
||||
|
||||
void RiscVJit::FlushAll() {
|
||||
void RiscVJitBackend::FlushAll() {
|
||||
gpr.FlushAll();
|
||||
fpr.FlushAll();
|
||||
}
|
||||
|
||||
bool RiscVJit::DescribeCodePtr(const u8 *ptr, std::string &name) {
|
||||
bool RiscVJitBackend::DescribeCodePtr(const u8 *ptr, std::string &name) const {
|
||||
// Used in disassembly viewer.
|
||||
if (ptr == dispatcher_) {
|
||||
name = "dispatcher";
|
||||
} else if (ptr == dispatcherPCInSCRATCH1_) {
|
||||
if (ptr == dispatcherPCInSCRATCH1_) {
|
||||
name = "dispatcher (PC in SCRATCH1)";
|
||||
} else if (ptr == dispatcherNoCheck_) {
|
||||
name = "dispatcherNoCheck";
|
||||
|
|
@ -220,81 +145,36 @@ bool RiscVJit::DescribeCodePtr(const u8 *ptr, std::string &name) {
|
|||
name = "saveStaticRegisters";
|
||||
} else if (ptr == loadStaticRegisters_) {
|
||||
name = "loadStaticRegisters";
|
||||
} else if (ptr == enterDispatcher_) {
|
||||
name = "enterDispatcher";
|
||||
} else if (ptr == applyRoundingMode_) {
|
||||
name = "applyRoundingMode";
|
||||
} else if (!IsInSpace(ptr)) {
|
||||
return false;
|
||||
} else {
|
||||
int offset = (int)GetOffset(ptr);
|
||||
int block_num = -1;
|
||||
for (int i = 0; i < blocks_.GetNumBlocks(); ++i) {
|
||||
const auto &b = blocks_.GetBlock(i);
|
||||
// We allocate linearly.
|
||||
if (b->GetTargetOffset() <= offset)
|
||||
block_num = i;
|
||||
if (b->GetTargetOffset() > offset)
|
||||
break;
|
||||
}
|
||||
|
||||
if (block_num == -1) {
|
||||
name = "(unknown or deleted block)";
|
||||
return true;
|
||||
}
|
||||
|
||||
const IRBlock *block = blocks_.GetBlock(block_num);
|
||||
if (block) {
|
||||
u32 start = 0, size = 0;
|
||||
block->GetRange(start, size);
|
||||
name = StringFromFormat("(block %d at %08x)", block_num, start);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
return IRNativeBackend::DescribeCodePtr(ptr, name);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool RiscVJit::CodeInRange(const u8 *ptr) const {
|
||||
return IsInSpace(ptr);
|
||||
}
|
||||
|
||||
bool RiscVJit::IsAtDispatchFetch(const u8 *ptr) const {
|
||||
return ptr == dispatcherFetch_;
|
||||
}
|
||||
|
||||
const u8 *RiscVJit::GetDispatcher() const {
|
||||
return dispatcher_;
|
||||
}
|
||||
|
||||
const u8 *RiscVJit::GetCrashHandler() const {
|
||||
return crashHandler_;
|
||||
}
|
||||
|
||||
void RiscVJit::ClearCache() {
|
||||
IRNativeJit::ClearCache();
|
||||
|
||||
void RiscVJitBackend::ClearAllBlocks() {
|
||||
ClearCodeSpace(jitStartOffset_);
|
||||
FlushIcacheSection(region + jitStartOffset_, region + region_size - jitStartOffset_);
|
||||
}
|
||||
|
||||
void RiscVJit::RestoreRoundingMode(bool force) {
|
||||
void RiscVJitBackend::RestoreRoundingMode(bool force) {
|
||||
FSRMI(Round::NEAREST_EVEN);
|
||||
}
|
||||
|
||||
void RiscVJit::ApplyRoundingMode(bool force) {
|
||||
void RiscVJitBackend::ApplyRoundingMode(bool force) {
|
||||
QuickCallFunction(applyRoundingMode_);
|
||||
}
|
||||
|
||||
void RiscVJit::MovFromPC(RiscVReg r) {
|
||||
void RiscVJitBackend::MovFromPC(RiscVReg r) {
|
||||
LWU(r, CTXREG, offsetof(MIPSState, pc));
|
||||
}
|
||||
|
||||
void RiscVJit::MovToPC(RiscVReg r) {
|
||||
void RiscVJitBackend::MovToPC(RiscVReg r) {
|
||||
SW(r, CTXREG, offsetof(MIPSState, pc));
|
||||
}
|
||||
|
||||
void RiscVJit::SaveStaticRegisters() {
|
||||
void RiscVJitBackend::SaveStaticRegisters() {
|
||||
if (jo.useStaticAlloc) {
|
||||
QuickCallFunction(saveStaticRegisters_);
|
||||
} else {
|
||||
|
|
@ -303,7 +183,7 @@ void RiscVJit::SaveStaticRegisters() {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::LoadStaticRegisters() {
|
||||
void RiscVJitBackend::LoadStaticRegisters() {
|
||||
if (jo.useStaticAlloc) {
|
||||
QuickCallFunction(loadStaticRegisters_);
|
||||
} else {
|
||||
|
|
@ -311,16 +191,16 @@ void RiscVJit::LoadStaticRegisters() {
|
|||
}
|
||||
}
|
||||
|
||||
void RiscVJit::NormalizeSrc1(IRInst inst, RiscVReg *reg, RiscVReg tempReg, bool allowOverlap) {
|
||||
void RiscVJitBackend::NormalizeSrc1(IRInst inst, RiscVReg *reg, RiscVReg tempReg, bool allowOverlap) {
|
||||
*reg = NormalizeR(inst.src1, allowOverlap ? 0 : inst.dest, tempReg);
|
||||
}
|
||||
|
||||
void RiscVJit::NormalizeSrc12(IRInst inst, RiscVReg *lhs, RiscVReg *rhs, RiscVReg lhsTempReg, RiscVReg rhsTempReg, bool allowOverlap) {
|
||||
void RiscVJitBackend::NormalizeSrc12(IRInst inst, RiscVReg *lhs, RiscVReg *rhs, RiscVReg lhsTempReg, RiscVReg rhsTempReg, bool allowOverlap) {
|
||||
*lhs = NormalizeR(inst.src1, allowOverlap ? 0 : inst.dest, lhsTempReg);
|
||||
*rhs = NormalizeR(inst.src2, allowOverlap ? 0 : inst.dest, rhsTempReg);
|
||||
}
|
||||
|
||||
RiscVReg RiscVJit::NormalizeR(IRRegIndex rs, IRRegIndex rd, RiscVReg tempReg) {
|
||||
RiscVReg RiscVJitBackend::NormalizeR(IRRegIndex rs, IRRegIndex rd, RiscVReg tempReg) {
|
||||
// For proper compare, we must sign extend so they both match or don't match.
|
||||
// But don't change pointers, in case one is SP (happens in LittleBigPlanet.)
|
||||
if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) {
|
||||
|
|
|
|||
|
|
@ -29,30 +29,23 @@
|
|||
|
||||
namespace MIPSComp {
|
||||
|
||||
// TODO: Separate.
|
||||
class RiscVJit : public RiscVGen::RiscVCodeBlock, public IRNativeJit, public IRNativeBackend {
|
||||
class RiscVJitBackend : public RiscVGen::RiscVCodeBlock, public IRNativeBackend {
|
||||
public:
|
||||
RiscVJit(MIPSState *mipsState);
|
||||
~RiscVJit();
|
||||
RiscVJitBackend(MIPSState *mipsState, JitOptions &jo);
|
||||
~RiscVJitBackend();
|
||||
|
||||
void RunLoopUntil(u64 globalticks) override;
|
||||
bool DescribeCodePtr(const u8 *ptr, std::string &name) const override;
|
||||
|
||||
bool DescribeCodePtr(const u8 *ptr, std::string &name) override;
|
||||
bool CodeInRange(const u8 *ptr) const override;
|
||||
bool IsAtDispatchFetch(const u8 *ptr) const override;
|
||||
const u8 *GetDispatcher() const override;
|
||||
const u8 *GetCrashHandler() const override;
|
||||
|
||||
void ClearCache() override;
|
||||
|
||||
JitBlockCacheDebugInterface *GetBlockCacheDebugInterface() override;
|
||||
void GenerateFixedCode() override;
|
||||
bool CompileBlock(IRBlock *block, int block_num, bool preload) override;
|
||||
void ClearAllBlocks() override;
|
||||
|
||||
protected:
|
||||
bool CompileTargetBlock(IRBlock *block, int block_num, bool preload) override;
|
||||
const CodeBlockCommon &CodeBlock() const override {
|
||||
return *this;
|
||||
}
|
||||
|
||||
private:
|
||||
void GenerateFixedCode(const JitOptions &jo);
|
||||
|
||||
void RestoreRoundingMode(bool force = false);
|
||||
void ApplyRoundingMode(bool force = false);
|
||||
void MovFromPC(RiscVGen::RiscVReg r);
|
||||
|
|
@ -114,27 +107,34 @@ private:
|
|||
void NormalizeSrc12(IRInst inst, RiscVGen::RiscVReg *lhs, RiscVGen::RiscVReg *rhs, RiscVGen::RiscVReg lhsTempReg, RiscVGen::RiscVReg rhsTempReg, bool allowOverlap);
|
||||
RiscVGen::RiscVReg NormalizeR(IRRegIndex rs, IRRegIndex rd, RiscVGen::RiscVReg tempReg);
|
||||
|
||||
// TODO: Maybe just a param to GenerateFixedCode().
|
||||
MIPSState *mips_;
|
||||
JitOptions &jo;
|
||||
RiscVRegCache gpr;
|
||||
RiscVRegCacheFPU fpr;
|
||||
IRNativeBlockCacheDebugInterface debugInterface_;
|
||||
|
||||
const u8 *enterDispatcher_ = nullptr;
|
||||
|
||||
const u8 *outerLoop_ = nullptr;
|
||||
const u8 *outerLoopPCInSCRATCH1_ = nullptr;
|
||||
const u8 *dispatcherCheckCoreState_ = nullptr;
|
||||
const u8 *dispatcherPCInSCRATCH1_ = nullptr;
|
||||
const u8 *dispatcher_ = nullptr;
|
||||
const u8 *dispatcherNoCheck_ = nullptr;
|
||||
const u8 *dispatcherFetch_ = nullptr;
|
||||
const u8 *applyRoundingMode_ = nullptr;
|
||||
|
||||
const u8 *saveStaticRegisters_ = nullptr;
|
||||
const u8 *loadStaticRegisters_ = nullptr;
|
||||
|
||||
const u8 *crashHandler_ = nullptr;
|
||||
|
||||
int jitStartOffset_ = 0;
|
||||
};
|
||||
|
||||
class RiscVJit : public IRNativeJit {
|
||||
public:
|
||||
RiscVJit(MIPSState *mipsState)
|
||||
: IRNativeJit(mipsState), rvBackend_(mipsState, jo) {
|
||||
Init(rvBackend_);
|
||||
}
|
||||
|
||||
private:
|
||||
RiscVJitBackend rvBackend_;
|
||||
};
|
||||
|
||||
} // namespace MIPSComp
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue