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40100 commits 81 branches 122 tags 700 MiB
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147 commits

Author SHA1 Message Date
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6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00
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921bd2391c riscv: Implement vi2s. 2023-07-29 19:02:15 -07:00
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e2765db4dc riscv: Implement division. 2023-07-29 19:02:15 -07:00
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f65b6fdb20 riscv: Remove incomplete block check. 
It shouldn't be necessary and bad things would happen anyway if it did.
 2023-07-29 19:02:15 -07:00
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8d60c10a64 riscv: Use jit address offsets directly. 
We'll have IR able to use block number or target offset.
 2023-07-29 19:02:15 -07:00
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e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
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a5a2671af3 irjit: Implement vf2ix. 
Used in LittleBigPlanet when playing intro movies.
 2023-07-29 18:01:08 -07:00
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df2462b1d9 irjit: Implement ll/sc. 
These occur more than I expected in LittleBigPlanet while loading.
 2023-07-29 17:57:44 -07:00
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a181f6d5b8 riscv: Add a comment for FMUL testing later. 2023-07-27 22:16:29 -07:00
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5122b0c78e riscv: Cleanup unnecessary fcr31 func. 
Don't need this, we use DYNAMIC.
 2023-07-25 20:33:56 -07:00
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0c9dce8ba8 riscv: Implement vec4 dot. 2023-07-25 20:33:56 -07:00
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23e9dffc68 riscv: Implement vec4 shuffle and init. 2023-07-25 20:33:56 -07:00
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4e17c59cc2 riscv: Implement simple vec4 ops via floats. 2023-07-25 20:33:56 -07:00
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df313bd296 riscv: Fix rounding mode setting. 2023-07-25 20:33:56 -07:00
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ca7a520a19 riscv: Implement FMul. 2023-07-25 20:33:56 -07:00
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9a9b371856 riscv: Implement FSign using FCLASS. 2023-07-25 20:33:56 -07:00
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05360d5c7a riscv: Implement simplest float ops. 2023-07-25 20:33:56 -07:00
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bb6fdd0246 riscv: Add floating point load/stores. 2023-07-25 20:33:56 -07:00
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7071884a47 riscv: Handle rounding mode and ctrl transfers. 2023-07-25 20:33:56 -07:00
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067a033dc0 riscv: Add FPU regcache. 2023-07-25 20:33:56 -07:00
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a8edf5fa24 riscv: Reduce bloat in jit fallbacks. 2023-07-25 19:42:04 -07:00
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b97b7f3663 riscv: Make some regcache methods private. 2023-07-25 19:42:04 -07:00
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b6f83ca969 riscv: Cleanup some pointerification flags. 2023-07-23 21:17:55 -07:00
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18c48681a8 riscv: Implement multiply instructions. 2023-07-23 18:01:50 -07:00
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7f4689e8fa riscv: Use direct SLI/SLIU instructions. 
Derp, I forgot these existed on RISC-V for a moment.
 2023-07-23 18:01:46 -07:00
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4100767b5e riscv: Optimize SetConst a bit. 2023-07-23 18:01:00 -07:00
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f7f7531500 riscv: Fix min/max normalization. 2023-07-23 18:01:00 -07:00
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34bfe93ea5 riscv: Fix block lookup issues. 2023-07-23 18:01:00 -07:00
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92694e765f riscv: Implement conditional moves. 2023-07-23 18:01:00 -07:00
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2c7da94bd1 riscv: Implement shifts and compares. 2023-07-23 18:01:00 -07:00
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5ed2f0d559 riscv: Implement logic ops. 2023-07-23 18:01:00 -07:00
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94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
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7aafa11d24 riscv: Implement conditional exits. 2023-07-23 18:01:00 -07:00
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8ee73264bf riscv: Correct depointerify on FlushAll(). 2023-07-23 18:01:00 -07:00
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720f868a10 riscv: Use R_RA as a temporary for calls. 
This is the most logical thing, since we're about to write it anyway.
 2023-07-23 18:01:00 -07:00
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76e3246065 riscv: Reduce jit codesize a bit. 2023-07-23 18:01:00 -07:00
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d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
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624caa2dea riscv: Implement the simplest exits. 2023-07-23 18:01:00 -07:00
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1dfedde741 riscv: Avoid needless save/load around compile. 2023-07-23 18:01:00 -07:00
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165169eb31 riscv: Implement load and store ops. 2023-07-23 18:01:00 -07:00
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c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
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05a2789cf4 riscv: Implement some simple assign instructions. 2023-07-23 18:01:00 -07:00
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c6c25af484 riscv: Add some safety to pointerifying. 
We have to clear the upper bits in case of sign extension or other things.
 2023-07-23 18:01:00 -07:00
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bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00
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4c1cc2dfdc riscv: Add a register cache for jit. 
Not yet actually used.  Might be buggy.
 2023-07-23 18:01:00 -07:00
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47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00
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e271e43ec5 riscv: Initial staffolding for IR based jit. 2023-07-23 18:01:00 -07:00