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https://github.com/fail0verflow/switch-coreboot.git
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d4480beaec
This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
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| .. | ||
| ac97.c | ||
| ac97audio.dts | ||
| ac97modem.dts | ||
| enable_usbdebug_direct.c | ||
| hda.c | ||
| hda.dts | ||
| ide.c | ||
| ide.dts | ||
| lpc.c | ||
| lpc.dts | ||
| Makefile | ||
| pci.c | ||
| pci.dts | ||
| sata.c | ||
| sata.dts | ||
| sb600.c | ||
| sb600.h | ||
| sb600_smbus.h | ||
| sm.c | ||
| sm.dts | ||
| stage1.c | ||
| stage1_reset.c | ||
| stage1_smbus.c | ||
| usb.c | ||
| usb.dts | ||
| usb2.dts | ||