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https://github.com/fail0verflow/switch-coreboot.git
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72c2e85313
pci_set_resources. There is no matching pci_bus_set_resources, so it's confusing to see the dev function in the bus structures. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
139 lines
4.5 KiB
C
139 lines
4.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "sb600.h"
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static void pci_init(struct device *dev)
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{
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u32 dword;
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u16 word;
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u8 byte;
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/* RPR 4.1 Enables the PCI-bridge subtractive decode */
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/* This setting is strongly recommended since it supports some legacy PCI add-on cards,such as BIOS debug cards */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 7;
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pci_write_config8(dev, 0x4B, byte);
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 5;
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pci_write_config8(dev, 0x40, byte);
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/* RPR4.2 PCI-bridge upstream dual address window */
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/* this setting is applicable if the system memory is more than 4GB,and the PCI device can support dual address access */
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byte = pci_read_config8(dev, 0x50);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x50, byte);
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/* RPR 4.3 PCI bus 64-byte DMA read access */
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/* Enhance the PCI bus DMA performance */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 4;
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pci_write_config8(dev, 0x4B, byte);
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/* RPR 4.4 Enables the PCIB writes to be cacheline aligned. */
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/* The size of the writes will be set in the Cacheline Register */
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 1;
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pci_write_config8(dev, 0x40, byte);
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/* RPR 4.5 Enables the PCIB to retain ownership of the bus on the Primary side and on the Secondary side when GNT# is deasserted */
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pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
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pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
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/* RPR 4.6 Enable the command matching checking function on "Memory Read" & "Memory Read Line" commands */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 6;
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pci_write_config8(dev, 0x4B, byte);
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/* RPR 4.7 When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT# */
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byte = pci_read_config8(dev, 0x4B);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x4B, byte);
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/* RPR 4.8 Adjusts the GNT# de-assertion time */
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word = pci_read_config16(dev, 0x64);
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word |= 1 << 12;
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pci_write_config16(dev, 0x64, word);
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/* RPR 4.9 Fast Back to Back transactions support */
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byte = pci_read_config8(dev, 0x48);
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byte |= 1 << 2;
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pci_write_config8(dev, 0x48, byte);
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/* RPR 4.10 Enable Lock Operation */
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byte = pci_read_config8(dev, 0x48);
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byte |= 1 << 3;
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pci_write_config8(dev, 0x48, byte);
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* RPR 4.11 Enable additional optional PCI clock */
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word = pci_read_config16(dev, 0x64);
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word |= 1 << 8;
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pci_write_config16(dev, 0x64, word);
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/* rpr4.12 Disable Fewer-Retry Mode for A11-A13 only. 0x64[5:4] clear */
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byte = pci_read_config8(dev, 0x64);
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byte &= 0xcf;
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pci_write_config8(dev, 0x64, byte);
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/* rpr4.14 Disabling Downstream Flush, for A12 only, 0x64[18]. */
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dword = pci_read_config32(dev, 0x64);
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dword |= (1 << 18);
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pci_write_config32(dev, 0x64, dword);
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/* RPR 4.13 Enable One-Prefetch-Channel Mode */
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dword = pci_read_config32(dev, 0x64);
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dword |= 1 << 20;
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pci_write_config32(dev, 0x64, dword);
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/* RPR 4.15 Disable PCIB MSI Capability */
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byte = pci_read_config8(dev, 0x40);
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byte &= ~(1 << 3);
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pci_write_config8(dev, 0x40, byte);
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/* rpr4.16 Adjusting CLKRUN# */
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dword = pci_read_config32(dev, 0x64);
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dword |= (1 << 15);
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pci_write_config32(dev, 0x64, dword);
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}
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struct device_operations sb600_pci = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_SB600_PCI}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase3_chip_setup_dev = sb600_enable,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pci_init,
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.reset_bus = pci_bus_reset,
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};
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