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https://github.com/fail0verflow/switch-coreboot.git
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2174dd2c78
Self-acked, as this was acked/committed in v2 already (r3680). Build-tested with the AMD dbm690t target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@948 f3766cd6-281f-0410-b1cd-43a5c92072e9
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SB600_H
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#define SB600_H
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#include <device/pci_ids.h>
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/* Power management index/data registers */
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#define PM_INDEX 0xcd6
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#define PM_DATA 0xcd7
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#define PM2_INDEX 0xcd0
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#define PM2_DATA 0xcd1
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void pm_iowrite(u8 reg, u8 value);
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u8 pm_ioread(u8 reg);
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void pm2_iowrite(u8 reg, u8 value);
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u8 pm2_ioread(u8 reg);
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void set_sm_enable_bits(struct device * sm_dev, u32 reg_pos, u32 mask, u32 val);
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void sb600_enable(struct device * dev);
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#endif /* SB600_H */
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