This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@955 f3766cd6-281f-0410-b1cd-43a5c92072e9
cleanups/fixes.
Fixup device tree code. Add/change methods as needed.
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
Self-acked, as this was acked/committed in v2 already (r3680).
Build-tested with the AMD dbm690t target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@948 f3766cd6-281f-0410-b1cd-43a5c92072e9
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@922 f3766cd6-281f-0410-b1cd-43a5c92072e9
affected. This mostly targets pci_*_config*() calls.
This is part of my quest to make existing code more readable without
looking up the meaning of magic numbers.
Ron pointed out that this enables better kscope usage.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@913 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@911 f3766cd6-281f-0410-b1cd-43a5c92072e9
a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is
present in Simnow, it is non functional.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@904 f3766cd6-281f-0410-b1cd-43a5c92072e9
23K, too large.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@893 f3766cd6-281f-0410-b1cd-43a5c92072e9
My apologies.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@881 f3766cd6-281f-0410-b1cd-43a5c92072e9
