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The change to Kconfig is self-acked.

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Add a depend clause so that we don't see these things on Geode. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
The other changes are:
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@753 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-13 02:44:46 +00:00
parent 6a732582c7
commit 2b83a9c158
3 changed files with 5 additions and 5 deletions
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2
arch/x86/Kconfig
View file

@ -133,6 +133,7 @@ config SMP
config IOAPIC
boolean
depends ARCH_X86
default 0
help
If you want to configure an IOAPIC, set this.
@ -209,5 +210,6 @@ config USBDEBUG_DIRECT
config APIC_ID_OFFSET
hex "APIC ID offset"
default 0x10
depends IO_APIC
help
This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting.

2
arch/x86/Makefile
View file

@ -183,7 +183,7 @@ STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \
compute_ip_checksum.c string.c
STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c
STAGE2_ARCH_X86_SRC += pci_ops_auto.c
STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
ifeq ($(CONFIG_PIRQ_TABLE),y)

6
arch/x86/resourcemap.c
View file

@ -47,8 +47,6 @@
/* NOTE: By doing the config write in this manner we guarantee that this
* will work in stage1 or stage2.
*/
#define pci_read_config32(busdevfn, where) pci_cf8_conf1.read32(busdevfn, where)
#define pci_write_config32(busdevfn, where, what) pci_cf8_conf1.write32(busdevfn, where, what)
void setup_resource_map_x_offset(const struct rmap *rm, u32 max,
u32 offset_bdf, u32 offset_pciio,
@ -77,10 +75,10 @@ void setup_resource_map_x_offset(const struct rmap *rm, u32 max,
dev <<= 3;
dev |= rm->pcm.fn;
dev += offset_devfn;
reg = pci_read_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where);
reg = pci_conf1_read_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where);
reg &= rm->pcm.and;
reg |= rm->pcm.or + offset_pciio;
pci_write_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where, reg);
pci_conf1_write_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where, reg);
}
break;
case TIO8: