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artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size)

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This changes SPD_NUM_COLUMNS from 0x8 back to 0xa, as it was originally when
copied over from another board, because 0x8 evaluates to 2kB, not 8kB, while 0xa
does the latter. 8kB is what the chip has and what is also set in our currently
used firmwares for DBE62.

This (combined with all the previous committed hard work from Ron before) fixes
memtest86+ freezes and hard reboots for me in quick 30 minute testing time,
while before it would freeze or reboot just into 50% of first test.

There is more to do to get the optimum RAM setup, but this should do for now -
the rest is just optimizing to quicker timings, while current ones in the fake
SPD are very conservative.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@757 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Mart Raudsepp 2008-08-13 17:21:09 +00:00
parent bfc217a8ce
commit bf5414f4ea
1 changed files with 1 additions and 1 deletions
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2
mainboard/artecgroup/dbe62/initram.c
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@ -65,7 +65,7 @@ static const struct spd_entry spd_table[] = {
{SPD_tRP, 0x58},
{SPD_PRIMARY_SDRAM_WIDTH, 8},
{SPD_NUM_BANKS_PER_SDRAM, 0x4},
{SPD_NUM_COLUMNS, 0x8},
{SPD_NUM_COLUMNS, 0xa}, /* 8kB */
{SPD_NUM_DIMM_BANKS, 0x1},
{SPD_REFRESH, 0x82},
{SPD_SDRAM_CYCLE_TIME_2ND, 0x0},