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UPSTREAM: superio/acpi: allow 3 I/O ranges on generic device
Some Super I/O logical devices have three I/O port ranges, such as the
GPIO on the IT8720F. Allow specifying a third I/O range. While here, fix
a typo in the I/O range description.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6dc205501ab40d8c57cbef0ce35653ddd7d6ac7b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: eeef6459a3
Original-Change-Id: Idad03f3881e0fbf2135562316d177972f931afec
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20024
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/531714
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
parent
115fc55b01
commit
562d605b73
2 changed files with 19 additions and 2 deletions
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@ -34,6 +34,8 @@
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#define PNP_IO0_LOW_BYTE IO0L
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#define PNP_IO1_HIGH_BYTE IO1H
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#define PNP_IO1_LOW_BYTE IO1L
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#define PNP_IO2_HIGH_BYTE IO2H
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#define PNP_IO2_LOW_BYTE IO2L
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#define PNP_IRQ0 IRQ0
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#define PNP_IRQ1 IRQ1
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#define PNP_DMA0 DMA0
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@ -32,10 +32,13 @@
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* SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG
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* bit (required if SUPERIO_PNP_PM_REG is defined)
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* SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o
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* resource (comma seperated, e.g. `0x02, 0x08`,
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* SUPERIO_PNP_IO1 The alignment and length of the second PnP i/o
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* resource (comma seperated, e.g. `0x02, 0x08`,
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* SUPERIO_PNP_IO2 The alignment and length of the third PnP i/o
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* SUPERIO_PNP_IRQ0 If defined, the first PnP IRQ register is enabled
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* SUPERIO_PNP_IRQ1 If defined, the second PnP IRQ register is enabled
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@ -96,6 +99,9 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
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#ifdef SUPERIO_PNP_IO1
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
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#endif
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#ifdef SUPERIO_PNP_IO2
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO2, IO2)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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IRQNoFlags (IR0) {}
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#endif
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@ -113,6 +119,9 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
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#ifdef SUPERIO_PNP_IO1
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PNP_READ_IO(PNP_IO1, CRS, IO1)
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#endif
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#ifdef SUPERIO_PNP_IO2
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PNP_READ_IO(PNP_IO2, CRS, IO2)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
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#endif
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@ -135,6 +144,9 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
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#ifdef SUPERIO_PNP_IO1
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
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#endif
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#ifdef SUPERIO_PNP_IO2
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO2, IO2)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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IRQNoFlags (IR0) {}
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#endif
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@ -152,6 +164,9 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
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#ifdef SUPERIO_PNP_IO1
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PNP_WRITE_IO(PNP_IO1, Arg0, IO1)
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#endif
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#ifdef SUPERIO_PNP_IO2
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PNP_WRITE_IO(PNP_IO2, Arg0, IO2)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
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#endif
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