- Fix TODO: restrict $1 to allowed values.
- Specifically exclude 'oem' board status directories.
- Exclude any directory that doesn't follow the date format to keep
the script from breaking again in the future if something it doesn't
recognize is pushed. Just ignore it for the wiki.
- Fix shellcheck warnings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I55cee2d8a6fc1a605d77f6cc6d9eb9e2defa4872
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27f3ce6337
Original-Change-Id: I2864f09f5f1b1f5ec626d06e4849830400ef5814
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18225
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433884
Without this motherboards that requires a non zero timeout for ps2
keyboards on SeaBIOS don't build when CONFIG_UPDATE_IMAGE is set.
An alternative way to achieve this file would be to include a cbfsfile
instead of calling cbfstool. That way the file gets updated/added both
both image update and regular build. A difficulty of that approach is
that it needs to convert a decimal to a binary in little endian
representation, which is not a trivial thing to do in a Makefile.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4814675b2f006656d1bd6f418e38afadee6aeb80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7218a1e754
Original-Change-Id: Icafba8d3e279a2e70e607abba81e3dbebfb55e4b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18231
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433883
If cmos is invalid, it doesn't make sense to read the value before
finding that out.
BUG=none
BRANCH=none
TEST=none
Change-Id: I99768c9fee002d965c8e98e36f5d385f9e9cd861
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e7a93fa65
Original-Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18236
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433882
The default macaddress in rt8168.c can be changed with a cbfsfile
called macaddress. This patch makes it possible to add such a file
using Kconfig at build time.
This also changes the name of the cbfsfile from "macaddress" to
"rt8168-macaddress" to avoid confusion.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib9c2286a9a382131cb1d1302202846b62c508f49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec74f45e72
Original-Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18088
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433881
Ubuntus default compiler flags for GCC [1][2] include `-Wformat
-Wformat-security`, causing errors similar like the one below.
```
CC romstage/northbridge/amd/amdht/ht_wrapper.o
src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify':
src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security]
printk(log_level, event_class_string_decodes[evtClass]);
^
[]
```
Fix that, by explicitly using a format string.
TEST=Built and booted on ASUS KGPE-D16.
[1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for
"fprintf, error: format not a string literal and no format arguments [-Werror=format-security"
[2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609.
Change-Id: Iff829bf83e1ead8537fbe5d7c5c6376bdd77f323
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f6776fa62c
Original-Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18208
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433880
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I6715126e4aaa9e133fefc2eaa9c7457654e99af3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe8a01b01a
Original-Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18227
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433878
me_cleaner is a tool to strip down Intel ME/TXE images by removing all
the non-fundamental code, while keeping the ME/TXE image valid and
suitable for booting the system. The remaining code (ROMP and BUP
modules) is the one responsible for the very basic initialization of
the ME/TXE subsystem and can't be removed.
This tool exploits the fact that:
* Each ME/TXE partition is signed individually and it is possible to
remove both the partition and the signature.
* The ME/TXE modules are not signed directly, instead they are hashed
and the list of their hashes is hashed again and signed: this
means that modifying a module doesn't invalidate the signature,
but only the hash of that single module.
* The modules hashes are checked only when the corresponding module
needs to be executed.
* The system can boot after the execution of the first module (BUP,
inside the FTPR partition), even if the subsequent stages fail.
Currently me_cleaner works on every Intel platform with Intel ME or
Intel TXE with the following limitations:
* Doesn't work when Intel Boot Guard is set in Verified Boot mode.
* Doesn't fully work on Nehalem yet.
* On Skylake and later generations, since the partitions' internal
structure has changed, me_cleaner leaves intact the FTPR
partition, removing all the the other partitions.
This tool has been tested on multiple platforms and architectures by
different users, and seems to be stable. The reports are available
here:
https://github.com/corna/me_cleaner/issues/3
A more in-depth description of me_cleaner is available here:
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
BUG=none
BRANCH=none
TEST=none
Change-Id: I4d697041a6d9df503d17a0e30fef4713120dddb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9bcc002f1e
Original-Change-Id: I9013799e9adea0dea0775b9afe718de5fc4ca748
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18203
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/432759
Make the code C89 compatible, which doesnt allow loop initial
declarations. Older compilers use C89 by default, so just declare the
variable outside.
BUG=none
BRANCH=none
TEST=none
Change-Id: If89c5f7ab563e8acde3150c57611a432d72509dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7385d14b1
Original-Change-Id: I3c5a8109e66f7a25687f4e4b2c72718d74276e04
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18196
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431984
Add support for Lenovo Thinkpad L520.
The files are generated by autoport,
and are successfully tested on the board.
L520 has got 4MiB flash chip, that contains a "slim" ME
with 1.2MiB only. The flash IC has to be desoldered, as
it won't be accessible in circuit. It is located on top
of the mainboard right under the touchpad.
Test-setup:
Extract the following blobs from vendor BIOS:
* Intel Flash Descriptor
* Intel Management Engine
* Intel VBios
The laptop has been externaly flashed. It was able to
turn on the display and load SeaBIOS.
Latest debian has been booted from harddisk.
Latest fedora has been booted from USB flash drive.
The following hardware has been tested and is working:
* Display using Option Rom
* PCIe wifi
* Ethernet
* Keyboard, trackpoint and touchpad
* Some Fn functions keys
* Volume Keys (except mic mute)
* Status LEDs
* Audio (headphone jack only)
* USB ports
* Native raminit dual channel (2 DDR3-1333 DIMMs tested)
* SATA cdrom
* SATA harddrive
Broken:
* Some Fn functions keys
* Microphone mute button
* Speakers (but headphone jack gives sound)
Untested:
* Expansion slot
* SD card slot
* Docking station
* Native gfx init
The EHCI debug port is the first one on the right side.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie7b248243339b52e6120c18ed217a740bc8992cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aae6e9cfe9
Original-Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18003
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431982
When .xcompile doesn't already exist, building libpayload fails because
the CC variable (et al) remain empty since .xcompile is only included
after the variables coming from there are evaluated.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie18787c4d871681de72e15ab6275a2f0003ed622
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b144a34c60
Original-Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18228
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/432758
It takes a long time for no gain: We don't need to update the
submodules, we don't need to fetch the revision, we don't need to find
the compilers, when all we want to do is to manipulate the .config file
or clean the build directory.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:432758
Change-Id: I2a2e65d1f5945885b43e32ecb8406f83f973c106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ffef882d8
Original-Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18182
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431983
This fixes building coreboot with -std=gnu11 on gcc 4.9.x
Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing
type.
BUG=none
BRANCH=none
TEST=none
Change-Id: I815127db725dd4bc3930e361d79d27a2a63eca80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06a629e4b1
Original-Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18220
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/431985
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1fb1184c5177437cc19824c14ec629440aaede80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dcc0aa84fa
Original-Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18039
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431980
o Fix indentation and other whitespace issues,
o Use `const` where applicable,
o Avoid retyping the same constant literals,
o Actually read PCI revision from the device (instead of using the
lowest class byte).
BUG=none
BRANCH=none
TEST=none
Change-Id: I74c9feb687e8e8b42aeeb4ed7265547f289fd427
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d37fa8d84d
Original-Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/18185
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431979
This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.
The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.
BUG=none
BRANCH=none
TEST=none
Change-Id: I28d51ae70b98abafbbfd68b38a59b00074bc89ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f1f0538cf
Original-Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18038
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431978
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=chrome-os-partner:62206
BRANCH=none
TEST=plug in a charger to either port and see charge status updated to
indicate charging in the power_supply_info tool and the Chrome OS UI.
Change-Id: Ie4a2c145714636c43cf74168c119442cb0663635
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e949faec1
Original-Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18209
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/431977
`libhwbase` is a SPARK library that contains some basic support for i/o
access, debugging, timers. Just what I put around `libgfxinit`, to make
it build standalone.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifba116e967357ed971aecd8a1d1661a493c0ca81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e09f8acdad
Original-Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/16948
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/430675
If compression failed, just store the uncompressed data, which is what
cbfstool does as well.
BUG=chrome-os-partner:62235
BRANCH=none
TEST=none
Change-Id: I41f911169f376be3dab1335d93e1b3ff68ad7377
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b46c4ecaba
Original-Change-Id: I67f51982b332d6ec1bea7c9ba179024fc5344743
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18201
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430741
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia83222824b338692fbcfe67318da1ca7173f46a7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: eee4f6b224
Original-Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18022
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/431292
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The devicetree settings were incorrect in a few places with
respect to the SOC and board design:
- IMVP8 VR workaround is for MP2939 and not MP2949 on Eve
- IccMax values are incorrect according to KBL-Y EDS
- USB2[6] is incorrectly labeled
- I2C touch devices do not need probed as they are not optional
- PCIe Root Port 5 should be enabled
- I2C5 device should not be enabled as it is unused
BUG=chrome-os-partner:58666
TEST=manually tested on Eve board
Change-Id: Ic863b0dce44a2f7f55b15a7a87513edc753d6a3c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 949e34c3ee
Original-Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18200
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431290
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to get quick boot speeds into recovery enable the
feature that allows for a separate recovery MRC cache.
This requires shuffling the FMAP around a bit in order to
provide another region for the recovery MRC cache. To make
that shuffling easier, group the RW components into another
sub-region so it can use relative addresses.
BUG=chrome-os-partner:58666
TEST=manual testing on eve: check that recovery uses the MRC
cache, and that normal mode does too. Check that if cache is
retrained in recovery mode it is also retrained in normal mode.
Also check that events show up in the log when retrain happens.
Change-Id: Id8e62117a9e679ef03e87a8563c377fc2a9a7c20
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: e00365217c
Original-Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18199
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431209
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The lpss_i2c driver is enabled in romstage, so the SOC needs to
export the pre-ram compatible I2C controller info, which for
skylake is in the bootblock/i2c.c file.
This was not causing a compiler error in normal use, but when
adding I2C debug code in romstage it failed to compile.
With this added, I can now do I2C transactions in romstage.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb17a32000c65a5f1577d3897ddaa869ef63ee32
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 4234ca2764
Original-Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18198
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431208
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the keyboard backlight as early in boot as possible to
provide a indication that the BIOS is executing.
Since this is bootblock it can't use the convenience function
for checking for S3 resume so just read the PM1 value from the
SOC and check it directly.
Use a value of 75% for the current system as that is visible
without being full brightness.
BUG=chrome-os-partner:61464
TEST=boot on eve and check that keyboard backlight is enabled
as soon as the SOC starts booting
Change-Id: I80274af9b3e032cc97403a180477b2d4742ad753
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: 367c9b328f
Original-Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18197
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/431207
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
They were sized to 32-bit alignment, this grows them to 64 bit-aligned.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie84b2c35b58f186bd8ae993e7ce298332858de05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bb036dcb
Original-Change-Id: I494b942c4866a7912fb48a53f9524db20ac53a8c
Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18165
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430618
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Removes the pre-defined VGA bios file and id because
the build system includes every vgabios.
Also make the VGA output primary by default
BUG=none
BRANCH=none
TEST=none
Change-Id: I851d602b470b1f0b504d07d5fe70fd58f20ae1a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c765ceff9
Original-Change-Id: I87d52ef2d1e151c6e54beba64316fe9043668158
Original-Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18181
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430617
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the ME is hidden (most likely because it was disabled), it cannot
be found until activate_me() is called.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifef2392e067c2075fafe6c83a3560dcedb2bf75d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8ad3c7b95
Original-Change-Id: Ie1f65f61eb131577d7254af582e2709660f4da27
Original-Signed-off-by: Dan Elkouby <streetwalrus@codewalr.us>
Original-Reviewed-on: https://review.coreboot.org/18149
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430616
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PP1800_S rail is turned off in S3. However, enabling internal
pullups on the pins which are connected to PP1800_S results in
leakage into the P1800_S rail. Fix this by disabling the internal
pullups on PP1800_S rail pins.
BUG=chrome-os-partner:61968
BRANCH=reef
TEST=measured leakage on PP1800_S rail. Gone with this patch.
Change-Id: I5c9a25ca617078a6ad48fe637abf0f397fda1ff5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa6482e88e
Original-Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808
Original-Signed-off-by: Aaron Duribn <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18189
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430614
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=None
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I0b3ec47e93b064f2195ec59bd9b5b8bc1927b3bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf68f2286c
Original-Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18163
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/430612
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per Audio PCH team recommendation the iDisplay Audio/SDIN2
should be disabled to bypass InitializeDisplayAudio() function
call. Display Audio Codec is HDA-Link Codec, which is not
supported in I2S mode
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Tested to verify that InitializeDisplayAudio() does not
get called.
Change-Id: I5900291ca4b2929db3e09277ffc3dce24d8de6fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 32997fb0bc
Original-Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18091
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430611
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
arm-trusted-firmware comes with another firmware for a coprocessor that
isn't AArch64. When building ATF, make sure to pass our arm(32) compiler
for that purpose.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0fb841a8d434389bc665fd6c133465dfcbba1fde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f34ca46fa6
Original-Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18024
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430717
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, it will print the function name as a prefix to the debug
output. Make it so that a null function name won't get printed, so
that it's possible to print little bits of debug output.
BUG=chromium:683391
BRANCH=none
TEST=build_packages --board=reef chromeos-firmware
Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431111
Reviewed-by: Julius Werner <jwerner@chromium.org>
This takes way too long to run - currently about 30 seconds to look
at the entire coreboot tree.
Change-Id: I5edc77bc808665ef9832970f5a6458ffe8c04ee1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e03fbced7
Original-Change-Id: I403934014b422528715ea95ff652babe5e18c88b
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/15976
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430716
This enables USB HID support in the veyron config, since it seems to
work correctly and is needed for interaction with depthcharge on devices
without an embedded keyboard (such as veyron_mickey).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic1ed2987074924fdab987974ad8e5bb7c9006f15
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e7f14bfae
Original-Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/17930
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430715
