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UPSTREAM: google/pyro: Add USB2 phy setting override

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In order to pass type A USB2 eye diagram,
USB2 port#0/#1 PHY register will need to be overridden.

port#0:
PERPORTPETXISET = 7
PERPORTTXISET = 1
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0

port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0

BUG=chrome-os-partner:59491
BRANCH=reef
TEST=emerge-pyro coreboot

Change-Id: Ie276baedb08c42d2b690080acbea5dc7f6e5e5cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0117924159
Original-Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18229
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433879
This commit is contained in:
Kevin Chiu 2017-01-25 23:06:23 +08:00 • committed by chrome-bot
parent 282007f52b
commit 44c4889d2e
1 changed files with 16 additions and 0 deletions
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16
src/mainboard/google/reef/variants/pyro/devicetree.cb
View file

@ -105,6 +105,22 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
# Override USB2 PER PORT register (PORT 0)
register "usb2eye[0]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 1,
.Usb20IUsbTxEmphasisEn = 3,
.Usb20PerPortTxPeHalf = 0,
}"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 2,
.Usb20IUsbTxEmphasisEn = 3,
.Usb20PerPortTxPeHalf = 0,
}"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF