The differential signal of DQS need keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it.But if it have PHY side ODT
connect at this time,it will change the DQS
signal level.So it need disable PHY side ODT
when do gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/448278
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Gru/Kevin use the 933M(actually 928M for better jitter) as max sdram freq,
while bob would use 800M.
It's normal some variants can't meet 928M SI requirement and hence want
use a lower freq as spec.
BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800M on bob
Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/420208
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Reviewed-on: https://chromium-review.googlesource.com/448277
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: I38a14abff2f619b2b11a8f3a12ce54f61028fb48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6295b8a57a
Original-Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18491
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446843
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.
BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional. Post-tuning measurement will be done
once a new firmware is released.
Change-Id: If6d7f8c77504c281bc4c0788ec0c5aa5c2607ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4d6ba180d
Original-Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18487
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446842
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
BUG=none
BRANCH=none
TEST=none
Change-Id: I31e2bda3b511f14fc46493f2d669b26a0329082d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a489237d5
Original-Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Original-Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18479
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446841
This fixes a warning that the new toolchain generates.
BUG=none
BRANCH=none
TEST=none
Change-Id: I110558801c33c2d82d56b8fd0a65b10f0e161605
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37e30aa624
Original-Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18485
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446840
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.
Change-Id: If0956204a6c6c266ea2383e29d8738b282caeb2e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 613350897d
Original-Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18466
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446839
This change is based on the following commit:
3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaee9f1240d01b1055b05320b2cfb2263d819f409
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08cf195f4c
Original-Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/18352
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446392
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when
the battery is nearly full and we switch from battery to AC by plugging
in the cable, the current rate will not drop to 0 immediately, but the
discharging state is cleared immediately.
This leads to the code trying to process an invalid rate value >0x8000,
leading to a displayed rate of >1000W.
This patch changes the logic to deal with these corner cases.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib0ec4d6bd5ecc128485e89449fca8021c58dd272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b798d7904
Original-Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18349
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446391
- Remove warnings about code using deprecated declarations such as:
plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup':
plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning:
'arm_gic_setup' is deprecated [-Wdeprecated-declarations]
include/drivers/arm/arm_gic.h:44:6: note: declared here:
void arm_gic_setup(void) __deprecated;
- Disable pedantic warnings to get rid of these warnings:
In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0:
plat/mediatek/mt8173/include/mcucfg.h:134:21: error:
enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant
expression [-Werror=pedantic]
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifb355b8d849d119692e0dd3ca11276ddce514089
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80c314d64a
Original-Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/17995
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/446390
This fixes warnings that the new toolchain generates.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie91f31785d2f3a78b96147b4f5a41e16b8d1142f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a6b1b258d2
Original-Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18308
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446389
Follow up to https://review.coreboot.org/#/c/18460/
BUG=none
BRANCH=none
TEST=none
Change-Id: I829c8546ac8d9883d973ff860986389d67b620c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96af0afcd7
Original-Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18475
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446387
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for poppy.
It enables the DPTF flag in the device tree for poppy. It also includes
the DPTF specific ASL file in the main DSDT definition.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I840b6d9fa170718b309c6a57c8d88e272bf92df5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d56fae18dc
Original-Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17926
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446386
Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
It was previously argumented this is copy-paste and never known
to be required for these more recent platforms:
https://review.coreboot.org/#/c/2706/
BUG=none
BRANCH=none
TEST=none
Change-Id: If3fb9ee922b6f202a5a9d5e654066b50507b0f01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57d4c30e22
Original-Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18330
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446385
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib193ed00b806294dc9210b566d7617aab6861190
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5c029f235
Original-Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18476
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446384
Camera and Imaging device should be enabled for camera usecase,
FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit)
expose the same as a config option in devicetree.cb
Also remove a redundant assignment for PchCio2Enable.
BUG=None
BRANCH=None
TEST=lspci should list 00:05:00
Change-Id: I8c1a35d1744079be768a985da0a7e8a54b9a268d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2c8a743d1
Original-Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18365
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446760
This enables some required Kconfig options when CONFIG_CHROMEOS is set.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib21f0b166ed9aac555e3b2a9418bf4d8a07e4b74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30d4604e5a
Original-Change-Id: I290902746c1ea19c8bcb69540e34fde09abb9adf
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/18448
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446759
This adds an oak libpayload config, that should fit all oak-based
devices such as elm.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id2fa6e80e6b7fd330a9e54adb639f437a9b1424d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a543d2ab9
Original-Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/18447
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446758
These parameters are probably the result of copying from the Thinkpad
X60 code.
BUG=none
BRANCH=none
TEST=none
Change-Id: I91aec0b2ccdafc1134183ad897c3123b2095fcdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00954f0815
Original-Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18290
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/446757
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
BUG=none
BRANCH=none
TEST=none
Change-Id: I422eda191c564e04331665413074b016175153ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97f542efc2
Original-Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18374
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/445835
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: I266e9f12db1c4824545871e6a0d1ac89f8d8255f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35f03d9027
Original-Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18298
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445834
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from coreboot/src/commonlib/fsp_relocate.c:18:
> coreboot/src/commonlib/include/commonlib/fsp.h:26: error:
> expected '=', ',', ';', 'asm' or '__attribute__' before
> 'fsp_component_relocate'
[...]
According to POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as opposed to utils code), as we
have a sys/types.h in src/include.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
BUG=none
BRANCH=none
TEST=none
Change-Id: I61d49c1e118c7d16d2f4ec1b600796c7b996c6f3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b89b2c50c5
Original-Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/18417
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445833
This is more consistent with newer Intel targets.
BUG=none
BRANCH=none
TEST=none
Change-Id: If00a2a24cb0d9f85913fb60ef87048a2feac844c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b29e0b70f8
Original-Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18371
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445832
There was a 'typo' where the subsystem id was set instead of the codec
vendor id. This caused the lynxpoint HDA codecs init to fail to find
the proper codecid verbs so codecs were never initialized. That caused
the headphones jack to not work.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6821c13910c1cd8c91ae6a70e15a222372b135dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 02756b8ffb
Original-Change-Id: I975031643fc42937ecaea2300639b90632543f67
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18411
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445829
The M.2 SSD is on the SATA port 3, which also required the DTLE setting
to be set.
This fixes issues with the M.2 SSD not being detected/stable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6922d284aeb07f2e32ced1cffaa47fcc1fd28637
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a462c157f8
Original-Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18409
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445827
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but
Browell supports up to 4 ports, so we need to support setting IOBP for
ports 2 and 3 as well.
The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only
guessed by looking at ports 0 and 1 and extrapolating from there.
Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work
so we can assume that port 2 and 3 magic numbers are valid, but having
someone confirm them (through non-public documents?) would be great.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8fc1e8ece37b7250cec54ba066b6293420ee6276
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 696ebc2dbc
Original-Change-Id: I59911cfa677749ceea9a544a99b444722392e72d
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/18408
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445826
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0.
For clarity, sdram-ddr3-samsung-2GB now is used by
- K4B4G1646D-BYK0
- K4B4G1646E-BYK0
- K4B4G1646Q-HYK0
BUG=chrome-os-partner:62131
BRANCH=veyron
TEST=emerge
Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/446197
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405)
Reviewed-on: https://chromium-review.googlesource.com/446300
This adds SDRAM entries for the following modules:
- Micron: DDMT52L256M64D2PP-107
- Hynix: H9CCNNNBKTALBR-NUD
They are compatible with Samsung K4E8E324EB-EGCF, so this just
copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used
in the comment near the top.
Notes on our "special snowflake" boards:
- veyron_danger's RAM ID is hard-coded to zero, so I skipped changes
involving the binary first numbering scheme.
- Rialto's SDRAM mapping is different, so I padded its SDRAM entries
to 24 to match other boards.
- veyron_mickey requires different MR3 and ODT settings than other
boards due to its unique PCB (chrome-os-partner:43626).
BUG=chrome-os-partner:59997
BRANCH=none
TEST=Booted new modules on Mickey (see BUG)
Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412328
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com>
Tested-by: Jiazi Yang <Tomato_Yang@asus.com>
(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6)
Reviewed-on: https://chromium-review.googlesource.com/446299
Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In order to allow GPIOs to be set/clear according to their polarity,
provide helper functions that check for polarity and call set/clear
SoC functions for generating ACPI code.
BUG=None
BRANCH=None
TEST=Verified that the ACPI code generated remains the same as before
for reef.
Change-Id: I0857d9e5625eca339f6185acea204fcfba901d25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf4845dd3a
Original-Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18427
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445821
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I54701329455709ce023bf363bdacdadf4f7d2639
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b9b593f2f
Original-Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18444
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446382
Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family14 northbridge with an SB800 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
(_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c
(_SB.PCI0.LPCB).
BUG=none
BRANCH=none
TEST=none
Change-Id: I707dcace91005120df4361e8bad749b2f165a308
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8a2c1fb17
Original-Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18402
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/446379
poppy board uses Maxim 98927 speaker codec and Realtek RT5663
for headset. Select the apropriate NHLT blobs to be packaged in CBFS.
Also, generate the required ACPI NHLT table for codec and the supported
topology in poppy.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=With the required driver support in kernel verify that
the Audio plays on on-board speakers and headset, recording
works from on-board mics and headset mics.
Change-Id: I8134a6978c2e21ff0d167a4ee038a1bc69df591f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f5446be4a
Original-Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed
Original-Signed-off-by: M Naveen <naveen.m@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18214
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445640
Add the audio devices to Eve mainboard:
- Describe Maxim 98927 speaker amps and RT5663 headphone codec
in ACPI so they can be enumerated by the OS.
- Supply NHLT binaries for MAX98927, RT5663, and DMIC_4CH.
BUG=chrome-os-partner:61009
TEST=manual testing on Eve P1 with updated kernel to ensure that
both speakers and headset are functional. DMIC support is
is still being worked on and is not yet functional.
Change-Id: Ib2965da2bb25c6d3b48d1da9aad2641b8eaf9189
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5492bfb55c
Original-Change-Id: I5243e35d159a0ed15c6004e94ba5a50b28cff0a9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18398
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/445639
Update GPIO controls and mainboard configurations for Rowan.
BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot
Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/430557
Reviewed-by: Julius Werner <jwerner@chromium.org>
