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UPSTREAM: mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state

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The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.

BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
     normal.

Change-Id: I38a14abff2f619b2b11a8f3a12ce54f61028fb48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6295b8a57a
Original-Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18491
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446843
This commit is contained in:
Aaron Durbin 2017-02-24 15:56:27 -06:00 • committed by chrome-bot
parent 84583ff805
commit 60a7bd05f0
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/reef/variants/baseboard/gpio.c
View file

@ -327,7 +327,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */
PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */
PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */
PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */
PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */