Provide some enums instead of unreadable comments that are usually
copied all over.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3286388b00ec6800f7a5b6a5c133d96e7d7e8162
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 503965f939
Original-Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19636
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528183
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
FSP_IMAGE_ID and FSP_IMAGE_REV are defined in `FspUpdVpd.h`. Check
against these to avoid mismatching definitions in coreboot and the
FSP blob.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0b936414f7c4d0c17800ea59c2bb3665cf700f6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e7947df462
Original-Change-Id: Ic86229e7f0c2d0525b8a79add292c6c81a349aa6
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19635
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528182
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Behavior matches with other dumps of inteltool.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3033ce4df78f611a85eede2dace4079483e26868
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c272a87f5c
Original-Change-Id: Id9755d251fc42185c9e8d574deb55c76e129b718
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19585
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528181
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We
detect that by checking the PCI device class.
The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported
now. For backwards compatibility, only dump port registers of ports
that are enabled in the Ports Implemented (PI) register.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2c8c108fc08f85edb3ddd3f2cb0ec66a8aa1a122
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: da94e171b5
Original-Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19584
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528180
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
We have to call pci_free_dev() for each device we allocated with
pci_get_dev(). Since that's not the case for `sb`, we can close
this TODO.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic80f45f717536f68774696e0b30cd8d7db9ebc45
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0660c6c1ff
Original-Change-Id: I1ef80c837263a205467f835156dcb8fa667d3a8f
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19587
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528179
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I66010e82a23d31ec4e99a3b5e810ea78fc4b88fc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ed9c9ce268
Original-Change-Id: Ia5ef6b04f01e381174a4d8f73ddafeb18d488803
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19583
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528178
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This is supposed to fill the `size[]` array with the actual sizes of
a device' MMIO ranges, but apparently isn't implemented for every
access method in libpci (we let the library choose one). It tells us
by clearing `PCI_FILL_SIZES` in the return value of `pci_fill_info()`
(which we don't check). Since we don't ever use `size`, we can just
make it clear and don't ask for it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I71907d75cae5d5acb5434a2e1f13fb6daaaca67e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ac826c8fd7
Original-Change-Id: I3fb9334472f1c7563a9e17910190f73affbe067a
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19582
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/528177
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A new variant copied from reef.
Allow override of the SKU.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5ad68505988d7c79d64b8654b3810669a4e7940
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b09933a2eb
Original-Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/524606
This typo existed in code before rewriting for using
defines and it's clearly visible after rewrite.
Previously it was writing to reserved area of GMBUS0 register,
while values are matching those of GMBUS1.
This line probably is a no-op since it's just sending the STOP
again (without an address set this time).
BUG=none
BRANCH=none
TEST=none
Change-Id: I7bcbaff545f45f0bcb6c23d7f4496f10681ef2eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34e10871f9
Original-Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e
Original-Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/16341
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/524605
set_var_mtrr() and get_free_var_mtrr() don't need to be guarded
against various stages. It just complicates code which lives
in a compilation unit that is compiled for multiple stages by
needing to reflect the same guarding. Instead, just drop the
declaration guard. earlymtrr.c is still just compiled for earlier
stages, but if needed it's easy to move to a mtrr_util.c that
is compiled for all stages.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2e78ef748b721b2a7ed08250ed0ffcda4dbffa08
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d86e0e6638
Original-Change-Id: Id6be6f613771380d5ce803eacf1a0c8b230790b6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20018
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/524598
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each rambi variant has a different USB port config.
Port data currently available for only candy and squawks;
other variants to be added once data obtained.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia5db0b81369ab60dbef8e59bfddd846bbd494950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74e1fb0b1a
Original-Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19974
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524597
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each jecht variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: I10e318e7bb6ea6ee3f4b0d5c210c4c7d639adce4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f069edb975
Original-Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19971
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524596
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each auron variant has a different USB port config.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic677f49c4355da471c50b55afc2a6351d8e0f27d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c3c7a1dcb
Original-Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19970
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/524595
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: I686dcc6b630a89d37e80276e9534923e8e6aad87
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b79d058767
Original-Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19969
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/524594
Include <arch/io.h> since functions use types defined in there.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icbfc9f69054b75bd94397da27ebff55b86378190
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7ca225a7e
Original-Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20004
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/524592
If CONSOLE_SPI_FLASH config is enabled, we write the cbmem
messages to the 'CONSOLE' area in FMAP which allows us to grab the
log when we read the flash.
This is useful when you don't have usb debugging, and
UART lines are hard to find. Since a failure to boot would
require a hardware flasher anyways, we can get the log
at the same time.
This feature should only be used when no alternative is
found and only when we can't boot the system, because
excessive writes to the flash is not recommended.
This has been tested on purism/librem13 v2 and librem 15 v3 which
run Intel Skylake hardware. It has not been tested on other archs
or with a driver other than the fast_spi.
BUG=none
BRANCH=none
TEST=none
Change-Id: I775e9fdbae152d57d659d300644a548bc5daed02
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c4b4ff3b1f
Original-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19849
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523981
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4f74548fd00577e1730c4535b8ea5c59b096f3ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cadd7c7ed3
Original-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19981
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523980
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
TEST: boot Windows on google/butterfly, observe battery data
reported correctly.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b79699fd993574addaf1a8cc0dfdb43e1f575b5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af4c0a431c
Original-Change-Id: I395cc7fbdf26c8cc816e47107e552c0533580fa1
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19961
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523979
sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f317e963dbc88a766be5da9e2266e328c4ed1ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a5c6201da
Original-Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19957
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523977
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3d0eab9eb780aff5e132a96fe436cae212426c69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3de6d38642
Original-Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19955
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/523976
This is to align with the SD_CD GpioInt setting in acpi
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: Id2c151cb8549e0c447c4a1494556f1cf6a55d0ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8cb70914ca
Original-Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20001
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523975
Currently, there is no macro to set GPIO interrupt trigger mode.
The purpose is to make coreboot set same trigger mode as GpioInt
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I3c9b8ac398708d6bde8a41044a77fed8acc8daed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4db78e39da
Original-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19992
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523974
Disable unused bridges that are not marked as hot-plugable.
Reduces idle power consumtion by ~200mWatt for each port.
Tested on Lenovo T430.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icb6e892125df29c05269814784fc1f1af96cefa6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4835a85c0
Original-Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19818
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523973
Add a method to get the state of a bridge device.
Return true if at least one enabled device on the secondary
bus is found.
Useful to disable non hotplugable bridges without any devices attached.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib399f149940b6686273bf7818463a3f25ee53f96
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a6909f88e9
Original-Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19817
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523972
The separate directory was the old way of handling variant boards.
Update bakersport_fsp to the new method. All of the other pieces
were already moved into bayleybay_fsp.
BUG=none
BRANCH=none
TEST=none
Change-Id: I43f64bde643de00db0eb4c0d165651732d33b333
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41807626e2
Original-Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19077
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/523971
Move the inline keyword in between the static keyword and the return
type.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0cc7d5d5c123202231946193d65e9541d2ee630f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cfbb815efd
Original-Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf
Original-Signed-off-by: Logan Carlson <logancarlson@google.com>
Original-Reviewed-on: https://review.coreboot.org/19991
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523970
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
BUG=none
BRANCH=none
TEST=none
Change-Id: I82dd1cfe7fc9f5635391431dd00b7bd67b8b916a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f848ed091e
Original-Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19956
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523968
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
BUG=none
BRANCH=none
TEST=none
Change-Id: If6176002997104b4d1470e6a0643b131262d965e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fab0a49019
Original-Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19973
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/523967
Add device/address stub for XHCI USB port 7.
Stub data will be supplemented by board-specific info
added in subsequent commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifd6dec3603caf24ab9214b35253845ea38446421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f9c46f0ebc
Original-Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19972
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523966
Add device/address stubs for XHCI USB ports 7/8, 10-15.
Stub data will be supplemented by board-specific info
added in subsequent commits.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic1ac51925175cf4828e3296958f3efb645e63ff5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2b1e996bbf
Original-Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19968
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/523965
Remove MONOTONIC_TIMER_MSR selection from mainboard
Konfigs, as it only does a reduntant selection of
HAVE_MONOTONIC_TIMER config, already selected under
skylake soc Kconfig.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaeecb8b10205ed68cad6890e42e6a5f1acf3c1b1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 051d6085e4
Original-Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20002
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/523964
Update camera sensor detail to OV 13858
Also update i2c address of OV5670
BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.
Change-Id: Ia097ac7da4c6dd0ceb30e930e1bd7c76cb155adc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: e7cb29493d
Original-Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20021
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523582
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This board is almost identical to D510MO, the only differences are
some differences in populated connections, CPU with less L2 cache and
a 10/100 Realtek NIC.
The vendor uses the very same binary for both D510M0 and D410PT.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie5dab03be5bf216297431ef539248087b8a8bd2c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 80d55b3ef3
Original-Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20000
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/522712
The IO region defined for EC_HOST_CMD_REGION1 was incorrectly
using EC_HOST_CMD_REGION0 for the range maximum so the region
was showing a minimum of 0x880 and a maximum of 0x800.
Both min and max should report the same value as this region
is fixed and cannot be relocated by the OS.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8e814348ba94b51d3cc52c7b94bd484e66e6a6b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ac86c37b2
Original-Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20007
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/522711
Use register name instead of magic value.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4e8550d3da6b9b0c9974b248339aacaa855a039a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 87b5ff0124
Original-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19954
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/522710
In get_region, ifdtool assigns a not-known-to-be-aligned
pointer to a uint32_t *. Now you know and I know that it is
almost certainly aligned, but clang on OSX doesn't like this,
and it's a dicey thing to do in any event, just waiting
to hit someone hard at some future date.
Assign the pointer to a void * and use memmove to copy
the value to a uint32_t.
This usage is more portable to all little-endian architectures,
now, but is still not endian-safe. I doubt we'll ever care.
BUG=none
BRANCH=none
TEST=none
Change-Id: I85be85b9e78c74dde72584f848441a6ddd0ec0c2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8db3c2a485
Original-Change-Id: Ifb2f260c3363ab0f5b4a59e5a4e0b5ecf049fa96
Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19921
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/522709
Looks like we're still building Strago firmware in ToT and it can get
compile failures from common code changes. Let's add it to the pre-CQ.
BRANCH=None
BUG=None
TEST=None
Change-Id: I26aee232251aeca656eb15624997142155adae22
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/520572
Reviewed-by: Don Garrett <dgarrett@chromium.org>
