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UPSTREAM: sb/intel/bd82x6x/early_usb: Use register name

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Use register name instead of magic value.

BUG=none
BRANCH=none
TEST=none

Change-Id: I4e8550d3da6b9b0c9974b248339aacaa855a039a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 87b5ff0124
Original-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19954
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/522710
This commit is contained in:
Patrick Rudolph 2017-05-28 13:57:04 +02:00 • committed by chrome-bot
parent 33d4ebe304
commit 81465afb57
2 changed files with 8 additions and 2 deletions
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6
src/southbridge/intel/bd82x6x/early_usb.c
View file

@ -37,7 +37,9 @@ early_usb_init (const struct southbridge_usb_port *portmap)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN,
DEFAULT_PMBASE | UPRWC);
for (i = 0; i < 14; i++)
write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
currents[portmap[i].current]);
@ -69,5 +71,5 @@ early_usb_init (const struct southbridge_usb_port *portmap)
pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
/* Relock registers. */
outw (0x0000, DEFAULT_PMBASE | 0x003c);
outw(0, DEFAULT_PMBASE | UPRWC);
}

4
src/southbridge/intel/bd82x6x/pch.h
View file

@ -113,6 +113,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
/* PM I/O Space */
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b