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UPSTREAM: mb/google/fizz: set SD_CDZ to edge trigger.

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This is to align with the SD_CD GpioInt setting in acpi

BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume

Change-Id: Id2c151cb8549e0c447c4a1494556f1cf6a55d0ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8cb70914ca
Original-Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20001
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523975
This commit is contained in:
Kane Chen 2017-06-01 20:08:48 +08:00 • committed by chrome-bot
parent 4aec5f8931
commit ed1aa558ff
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/google/fizz/gpio.h
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@ -42,7 +42,8 @@ static const struct pad_config gpio_table[] = {
/* ESPI_IO3 */
/* ESPI_CS# */
/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */
/* PIRQA# */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CDZ */
/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,
EDGE), /* SD_CDZ */
/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */
/* ESPI_CLK */
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */