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UPSTREAM: soc/broadwell: add missing USB port defs

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Add device/address stubs for XHCI USB ports 7/8, 10-15.
Stub data will be supplemented by board-specific info
added in subsequent commits.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ic1ac51925175cf4828e3296958f3efb645e63ff5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2b1e996bbf
Original-Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19968
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/523965
This commit is contained in:
Matt DeVillier 2017-04-17 18:35:00 -05:00 • committed by chrome-bot
parent b4bdccbc6c
commit 2c9186e4af
1 changed files with 8 additions and 1 deletions
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9
src/soc/intel/broadwell/acpi/xhci.asl
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@ -355,12 +355,19 @@ Device (XHCI)
{
Name (_ADR, 0x00000000)
// How many are there?
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5
Device (PRT7) { Name (_ADR, 7) } // USB Port 6
Device (PRT8) { Name (_ADR, 8) } // USB Port 7
Device (SSP1) { Name (_ADR, 10) } // USB Port 10
Device (SSP2) { Name (_ADR, 11) } // USB Port 11
Device (SSP3) { Name (_ADR, 12) } // USB Port 12
Device (SSP4) { Name (_ADR, 13) } // USB Port 13
Device (SSP5) { Name (_ADR, 14) } // USB Port 14
Device (SSP6) { Name (_ADR, 15) } // USB Port 15
}
}