UPSTREAM: soc/intel/apollolake: Add config for cpu base clock frequency

Add config for cpu base clock frequency(Mhz), use and
clean up code.

BUG=none
BRANCH=none
TEST=none

Change-Id: I6399d457dafe042ae572b125e382d95792bf0979
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 22b2c793e3
Original-Change-Id: I724c48c11796aa942295d4f19cc629d4c13647e1
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20017
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/524601

src/soc/intel/apollolake/Kconfig

@@ -322,4 +322,8 @@ config IFD_CHIPSET
 	string
 	default "aplk"
 
+config CPU_BCLK_MHZ
+	int
+	default 100
+
 endif

src/soc/intel/apollolake/include/soc/cpu.h

@@ -32,8 +32,6 @@ void enable_untrusted_mode(void);
 #define CPUID_APOLLOLAKE_A0	0x506c8
 #define CPUID_APOLLOLAKE_B0	0x506c9
 
-#define BASE_CLOCK_MHZ		100
-
 /* Common Timer Copy (CTC) frequency - 19.2MHz. */
 #define CTC_FREQ		19200000
 

src/soc/intel/apollolake/tsc_freq.c

@@ -26,7 +26,7 @@
 unsigned long tsc_freq_mhz(void)
 {
 	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
-	return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+	return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff));
 }
 
 void set_max_freq(void)