We need to rewrite libtool's files (foo.la) a couple of times so it
knows where to look
(while still whining that $DESTDIR$TARGET != $TARGET. well, duh.)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib444c60924e48f5adcefeecccdb0a24250075b12
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 790aab6c77
Original-Change-Id: I54cafd47c76d855222ba905b5eb4533a23bdfd34
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19463
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/490074
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=b:35586577
BRANCH=none
TEST=On a poppy board that has the VBUS rework applied, plug in a charger to
either port and see charge status updated to indicate charging in the
power_supply_info tool and the Chrome OS UI.
Change-Id: I07ca5d7383e5e6b014a6b35c2b7c5ba6edd1234e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb368db2a4
Original-Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a
Original-Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19441
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/490073
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
If the mainboard supports VBNV, call init_vbnv_cmos() instead of
the normal init_cmos(). The VBNV version does some VBNV pre
and post setup around the normal init_cmos().
BUG=none
BRANCH=none
TEST=none
Change-Id: I6754b2789175ea9bd61235bcecdf1ffdc7fccb42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 956a58e4fe
Original-Change-Id: I34b02409019b945cd68c830e006e99338643f29c
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19399
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490072
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.
The bridge was disable in the following commit [1]
commit a8e1168064
Author: Stefan Reinauer <stepan@coresystems.de>
Date: Wed Mar 11 14:54:18 2009 +0000
This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:
but unfortunately it was not noted which system this caused
problems with.
[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6
BUG=none
BRANCH=none
TEST=none
Change-Id: I6020ee2d6fbd01dc6a0a5f9d0cedb97056d0cfb2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2b7bd859a
Original-Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/2706
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/490071
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This reverts commit e7394ca903.
Configuration register for ACPI PM base address is initially configured
inside the PI blob. Therefore, the value of HUDSON_ACPI_IO_BASE needs
to be the same as DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS used in the build
of binaryPI blob.
BUG=none
BRANCH=none
TEST=none
Change-Id: I02857c5299493d0723c86c46cd5a3a46b46973f5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 771e8c114f
Original-Change-Id: I36700e49e21cc675e8e22b06efffb40e9c1e4236
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19454
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/490067
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Replace ram_check with quick_ram_check, because ram_check is slow and
is destructive for dram content.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibb484e1894fa86c1f47a03a61ff4d0ace1452838
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58ab3bed82
Original-Change-Id: I5fb1bfe711549aabb6e597bda22848988a7e9cbe
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19416
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/488283
MMA blobs are SOC specific (not board). So far MMA
is supported by big cores (SKL and KBL).
BUG=none
BRANCH=none
TEST=none
Change-Id: I511652c7f5492f52ff2446bfc214d92ed79c1e7c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebb7994263
Original-Change-Id: I922789a2a12d55360624dd6de15ab9f0bb5f0acf
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19260
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488281
Add a function to send the TPM decode to the SPI interface.
Enables use of SPI TPMs on Hudson mainboards.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7ae140e18c3e0a3c43e72dcb899ee8bd68beb945
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6fcaaef614
Original-Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19402
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/488060
Change spaces to tabs and do general whitespace cleanup.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia4732dca1545b784de5c839e074eb9122ff2b7e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c1f32336e6
Original-Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19401
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/488059
Move the ACPI IO registers from 0x800 to 0x600 to avoid the
IO space required by the Google EC, also at 0x800.
This shouldn't have any conflicts on other AMD systems.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae32c2450667da500771d9aada2e121da0c467a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7394ca903
Original-Change-Id: Iac7388c15e899277fd506fb37965164488358335
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19171
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488058
Add a function to enable LPC IO decode AKA WideIO.
This can enable up to 3 regions, which may be 512 or 16
bytes wide.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id7b09a5df91744b8a0cdcf86a3d80d28880db3d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f962aa52d6
Original-Change-Id: I2bed3a99180188101e00b4431d634227e488cbda
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19160
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488057
It turns out that there are quite a few other projects that can access
the CBMEM console by now. If we ever want to make another structural or
behavioral change to it, we need to know where these implementations are
so we can make sure they're all getting updated. Let's try to build a
comprehensive list in the file that should be the source of truth for
all (coreboot's own implementation).
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae97ac8306e640fde6bd2300f62b7fcaf960eea0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a915cea289
Original-Change-Id: Ia3d6a87230f5bfdde9d812bc7154e22880c1377a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19439
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/488056
Add a basic GPIO get function.
Note that GPIO set, ACPI/GPE, and other features should come
in future commits. Future changes to be modeled on the other soc/
gpio functions.
BUG=none
BRANCH=none
TEST=none
Change-Id: I816c7a6f50d25ef70ae7c87a2642d746d09b6f6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dae95f0dfe
Original-Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19159
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488055
The silicon specific mainboard_romstage_entry() in amd/cpu/car.h,
which is used by all AMD silicon car code, caused a conflict.
Move the silicon specific defines to silicon header files. Also,
no longer include car.h in the romstage file.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1b0d54a7697be3c985693020078200705f08d1b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4aad421e81
Original-Change-Id: Icfc759c4c93c8dfff76f5ef9a1a985dd704cfe94
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18769
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488054
These files are actually indentical, but unfortunately, the formatting
was changed without caring for the already present files. Fix that. Use
the license formatting where less lines are used.
The next step is to put that in a common location.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7b8ec432871845f5ae16f43508f8e922ada35e16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d06c51895e
Original-Change-Id: Iecb263b9d321a33e64988b315220893df2e0045c
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/19423
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/488053
According to the comment above the default should dump the EC ram,
though is never reached since the variable 'write_addr' is not 0, but
initialized at -1.
Also removes brackets around one line statement below if to make
checkpatch.pl happy.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6e055b5ad1c2bbd62ac450a9c38267fd92fc884e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 878c2de41b
Original-Change-Id: I390996b253f2f20682cd9ab2d4f560de6eccfc57
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19152
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/488052
When setting output to verbose, it incorrectly reports that it times
out on every command.
TESTED on Thinkpad X60.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibff3a5d8b073ab5fb40d5fbfda2137a725574e02
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2873a4aea4
Original-Change-Id: I24f05f0c165462d5ba2604c7e2fe139400683275
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19151
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/488051
Utilize the postcar stage for tearing down CAR and initializing
the MTRRs once ram is up. This flow is consistent with apollolake
and allows CAR_GLOBAL variables to be directly accessed and no
need for migrating CAR_GLOBAL variables as romstage doesn't
run with and without CAR being available.
BUG=none
BRANCH=none
TEST=none
Change-Id: I78458fefac96d714eeacc3832a2c4818d2fcd016
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79f0741f81
Original-Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19335
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488049
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0409e8e9d6a203254a9f9b749de5cab70dfc842
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4d7abc0d4
Original-Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19333
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/488047
The console log level variable doesn't really rely on ROMSTAGE_CONST
proper. Instead, the mutability of the variable is based on the current
implementation of ROMSTAGE_CONST (__PRE_RAM__). As such directly
use that logic for the code. In addition, refactor the code to let
the compiler and linker optimize out accesses instead of using
the pre-processor.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie38d062b92b9bcd7bf7faf88a9495c52c0d5488d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4003950881
Original-Change-Id: I44bcc409266ef52b9be29f75efde73a6707a53f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/488046
The ramstage-c-ccopts variable needs to be double dereferenced
for the cbfs-files-processor-struct handler so all the ccopts
are included since the ramstage-c-ccopts is fully constructed
later by another function. Without this not all the flags
are present on the command line.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic3d0b9f7ddf2cd0d3b542bd35a2d7e209a77c364
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42bcd13c75
Original-Change-Id: I5425b3c1f23d767c61f654dd287584403f85d719
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19380
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/488045
Delete the write to PM register 0xee. This register is not
listed in the current BKDG and S4 is not currently supported
on this APU.
NDA document #47517 "A55/.../A85X fusion Controller Hub Register
Reference Guide" provides some clues on the intent of this write.
This register has always been observed to power on with a value
of 0x08 so the write has no effect.
This should be revisited again when SMI and PSP fully implement
the support required for S3.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7c01148c21a07b51848f59e85161cb30450fa7a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e438af995
Original-Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18494
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486780
Create new functions similar to read and write of other sizes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I02df458e0af93e614768636ead2ab693ccbca90a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efd077ac52
Original-Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19394
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486779
The SD/MMC support is broken into several pieces. There are three main
data structures:
* sdhci_ctrlr - This is SDHCI controller specific and defined in
include/device/sdhci.h
* sd_mmc_ctrlr - This contains generic controller management data and
defined in include/device/sd_mmc_ctrlr.h
* storage_media - This contains the flash storage device management data
and is defined in include/device/storage.h
The SD/MMC driver consists of several components:
* SDHCI controller code
* bouncebuf.c
* bouncebuf.h
* pci_sdhci.c
* sdhci.c
* sdhci.h
* sdhci_adma.c
* sdhci_display.c
* Flash storage device support
* mmc.c
* mmc.h
* sd.c
* sd_mmc.c
* sd_mmc.h
* storage.c
* storage.h
* storage_erase.c
* storage_write.c
Kconfig values enable various portions of the controller and storage
drivers to be built to reduce the overall size of what is included in
the final image.
Full read/write/erase operations are provided for those platforms which
want to take advantage. It is also possible to build the driver to
perform initialization only. By default, this driver is not included in
any platform, platforms must specifically select DRIVERS_STORAGE to add
the SD/MMC support.
After this patch is reviewed and merged, there are some additional
patches:
* Common CAR storage area - Use a predefined region of CAR to pass data
structures between bootblock through to romstage. This allows early
stages to preform the SD/MMC device initialization and later stages
to use the SD/MMC device without further initialization. The example
code initializes the SD/MMC device in bootblock and uses the SD/MMC
device in romstage without further initialization.
* CBMEM ID - Add a CBMEM ID value for the data structures so that they
may be passed from romstage to ramstage and eventually the payload.
The example uses the SD/MMC device in ramstage without further
initialization.
* Move the SD/MMC driver into commonlib
* Have libpayload build the SD/MMC driver from commonlib. The intent
is to pass the controller state to libpayload so that the SD/MMC
device can be used without further initialization.
* On some platforms, have depthcharge use the commonlib SD/MMC driver
History:
Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot
and make the following changes:
* Removed #include "config.h" from mmc.c, allow the lint tests to pass.
* Move include files from drivers/storage into include/device.
* Rename mmc.h to storage.h.
* Add the Kconfig and Makefile and make edits to get the code to build.
* Add support to initialize a PCI controller.
* Fix formatting issues detected by checkpatch.
* Fix data flow issues detected by checkpatch.
* Add the missing voltage (MMC_VDD_35_36) into the voltage mask.
* Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*.
* Replace printf with sd_mmc_error.
* Add sdhc_debug, sdhc_trace and sd_error macros.
* Add Kconfig values to enable storage device debugging and tracing.
* Add tracing and debug support to the SDHCI driver.
* Allow SOC to override more controller features.
* Split out ADMA support.
* Move 1V8 support into SOC routine.
* Move HS400 support into SOC routine.
* Rework clock handling.
* Change all controller references to use ctrlr.
* Update the voltage handling.
* Update modes of operation.
* Move DMA fields into MmcCtrlr.
* Update bus width support.
* Change MMC_TIMING_* to BUS_TIMING_*.
* Rename MMC_MODE_ to DRVR_CAP.
* Move quirks into ctrlr->caps.
* Associate removeable with the controller.
* Statically allocate MmcMedia.
* Replace the SdhciHost structure with the MmcCtrlr structure.
* Split the code to support other SD/MMC controllers.
* Split out erase and write support.
* Update the code to be more consistent with the coreboot coding style.
* Only expose calling APIs.
* Divide up mmc.c into 4 modules: MMC, SD, storage card, common code.
* Update debug and error messages.
* Add partition support.
* Display clock frequencies once in MHz.
* Remove mmc_send_cmd, use ctrlr->send_cmd instead.
* Handle error from sd_send_op_cond.
* Allow mainboard to control delays around CMD 0.
* Support command logging.
* Mainboard may set delay after SD/MMC command.
* Display serial number with sd_mmc_trace.
* Remove cmd set parameter from mmc_switch.
* Display errors for timeout and comm errors.
* Add LED support.
* Move 64bit DMA flag into ctrlr->caps.
* Rework PIO transfer routine.
* Add HS200 bus tuning.
* Add support for HS400.
* Use same format for HS400, HS200 and HS52.
* Reduce storage_media structure size
* Add routine to update code pointers
* Add display of storage setup
* Display controller setup
TEST=Build and run on Reef and Galileo Gen2
Change-Id: I2666347879066a8920494feced97e6bb7218d757
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eef40eb2a9
Original-Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19208
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/486775
Add a Kconfig value to indicate coreboot builds.
Add prototypes and definitions for:
* dma_coherent
* dma_malloc
* xmalloc
* xzmalloc
Move prototype for memset into stdlib.h from string.h to eliminate build
breaks.
TEST=Build and test on Galileo Gen2
Change-Id: I43d69466a55f18f179b56bd9cd9d5ff8ea058ad8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb70c40f2e
Original-Change-Id: Ib2eb2ca143b0538bdd1863e628af4c1948bc0f8c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19207
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/486774
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3c561f2bcffeb7e76159c529049c7aaeb7143a13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00fd3ff507
Original-Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19337
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486761
There is no need to override CBFS_SIZE since there is no additional
firmware needed on the flash.
Also due to it having a description CBFS_SIZE was displayed twice in
menuconfig, which is fixed by this.
BUG=none
BRANCH=none
TEST=none
Change-Id: I14d3948338e1cf4b644bcd915f21d7a62ef13730
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e1194567f
Original-Change-Id: I1a8e2e458ac4d420f3fd4628c2805b6d4e2ee529
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19331
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486760
Tested on X230 with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.
This is a copy-paste of I8e02c8003ff745d05ee272c59377174847f5219c.
BUG=none
BRANCH=none
TEST=none
Change-Id: If193f6fa4d997e04d8b18a602dd5904e6c6abbfc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 166eaca9d8
Original-Change-Id: I8f270d558668c1fe41bcdcc7d6d2aa7f053c85b6
Original-Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19412
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486759
Lid switch is not available.
Hence report lid state as always open.
BUG=none
BRANCH=none
TEST=none
Change-Id: I64d1c491e583bbdc3e48e1d87b39eb2043b3e71e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3a117908c
Original-Change-Id: Ia9c82c3ad323912bad51cf55ed80a37b3110b1ef
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19219
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/486758
Use spi_setup_slave to fill up the spi_slave structure with
pointer to spi_ctrlr structure which can then be used to perform all
spi operations.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5b6a8bdfdb2340abdebe17cfcc52346f7fcb7f9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e49b0a2c5
Original-Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19385
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486755
Depend on I2C_TPM to prevent showing the menu entry on systems
that do not have an I2C TPM installed.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idb9e04bb8e16bcba294403cd718eecb2504547ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d74836488
Original-Change-Id: I7cd647c9c7e9721eab96ab64b844a882f156ee68
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19374
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/486753
Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.
BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
We are currently working on bringup and have no
hardware to test on yet.
Change-Id: I668d51f613176b5d46b71830c169c317abc4b1d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 031c818633
Original-Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19205
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486750
This board was added while the latest libgfxinit changes were in review.
Update to make it compile again and sanitize the port list.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia0cfaad77bdda3b09771a4d7184f1fdb0f58f4af
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7f28700f4
Original-Change-Id: I81b96e225945a8f8e47b64cefea91eb2747675ca
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19353
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://chromium-review.googlesource.com/486749
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ied3d7e52f9a905e10b07a65b501e7ba5e0a950fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b4d2cfc73
Original-Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19291
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/486748
MMA blobs internal version 2.1018 adds more tests.
This patch updates the script to accommodate that
change. MMA blobs are part of chrome private
repository.
BUG=none
BRANCH=none
TEST=none
Change-Id: I66ea2a64c0ef268cd624909413123dc06a0d06ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0bb611d125
Original-Change-Id: Iff660fdfdfcd7acc3820c5550740276be6213877
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19259
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486747
