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UPSTREAM: mb/intel/d510mo: Add romstage timestamps

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BUG=none
BRANCH=none
TEST=none

Change-Id: I7fab2c0634be26abb33c99d4048d31e1cebaf811
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0c0b79689a
Original-Change-Id: I324edce44ad82217ac1fba177f4a0bb3c799308c
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19426
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/488284
This commit is contained in:
Arthur Heymans 2017-04-22 16:48:58 +02:00 • committed by chrome-bot
parent 26e1568faa
commit 543102f9e7
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/intel/d510mo/romstage.c
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@ -33,6 +33,7 @@
#include <arch/stages.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0)
@ -105,6 +106,9 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
int boot_path;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
@ -137,7 +141,9 @@ void mainboard_romstage_entry(unsigned long bist)
}
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
printk(BIOS_DEBUG, "Memory initialized\n");
post_code(0x31);