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UPSTREAM: i82801gx: Enable PCI-to-PCI bridge

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Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.

Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.

The bridge was disable in the following commit [1]

    commit a8e1168064
    Author: Stefan Reinauer <stepan@coresystems.de>
    Date:   Wed Mar 11 14:54:18 2009 +0000

        This patch contains some significant updates to the i82801gx component and will
        be required for a series of later patches. Roughly it contains:

but unfortunately it was not noted which system this caused
problems with.

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6

BUG=none
BRANCH=none
TEST=none

Change-Id: I6020ee2d6fbd01dc6a0a5f9d0cedb97056d0cfb2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2b7bd859a
Original-Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/2706
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/490071
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2013-03-13 11:12:56 +02:00 • committed by chrome-bot
parent 53d4be5cf3
commit 03c4468697
1 changed files with 0 additions and 9 deletions
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9
src/southbridge/intel/i82801gx/pci.c
View file

@ -58,7 +58,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
#undef PCI_BRIDGE_UPDATE_COMMAND
static void ich_pci_dev_enable_resources(struct device *dev)
{
const struct pci_operations *ops;
@ -76,16 +75,8 @@ static void ich_pci_dev_enable_resources(struct device *dev)
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/* If we write to PCI_COMMAND, on some systems
* this will cause the ROM and APICs not being visible
* anymore.
*/
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
#else
printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
}
static void ich_pci_bus_enable_resources(struct device *dev)