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UPSTREAM: mainboard/amd/gardenia: Remove PMxEE write on S4 resume

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Delete the write to PM register 0xee.  This register is not
listed in the current BKDG and S4 is not currently supported
on this APU.

NDA document #47517 "A55/.../A85X fusion Controller Hub Register
Reference Guide" provides some clues on the intent of this write.
This register has always been observed to power on with a value
of 0x08 so the write has no effect.

This should be revisited again when SMI and PSP fully implement
the support required for S3.

BUG=none
BRANCH=none
TEST=none

Change-Id: I7c01148c21a07b51848f59e85161cb30450fa7a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e438af995
Original-Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18494
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486780
This commit is contained in:
Marc Jones 2017-02-23 22:06:01 -07:00 • committed by chrome-bot
parent 3caa405926
commit b63ae3a265
1 changed files with 0 additions and 5 deletions
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5
src/mainboard/amd/gardenia/romstage.c
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@ -66,11 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* TODO: Disable cache is not ok. */
disable_cache_as_ram();
if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
post_code(0x50);
copy_and_run();