Depending on the commit to build, depthcharge may have a different
target name (depthcharge vs. depthcharge_unified). Add some logic
to determine which name should be used based on the commit ID
being requested.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic008bb20846b55640b97140b1c08ddf7eb0f92a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f470c7a7e
Original-Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18269
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435808
Drop the _unified moniker from the depthcharge build. The payload
and coreboot have drifted out of sync and there is no longer a
non-unified depthcharge.
This patch corresponds with the depthcharge change:
https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739
BUG=none
BRANCH=none
TEST=none
Change-Id: Id6d090edec4fe1a8194bfabee5afb8b8f42f200e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e33e27a46
Original-Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18268
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435807
Different compiler versions use a different C language standard by
default.
GCC 4.9 uses GNU89 by default [1], while GCC 5.x uses GNU11 [2].
The discussion on the mailing list in thread *[RFC] Setting C99 by
default* [3] resulted in the preference of C11, which results in build
errors.
So explicitly set it to GNU11, which is also what the current coreboot
toolchain with GCC 5.3 is using.
[1] https://gcc.gnu.org/onlinedocs/gcc-4.9.4/gcc/C-Dialect-Options.html
[2] https://gcc.gnu.org/onlinedocs/gcc-5.4.0/gcc/Standards.html
[3] https://www.coreboot.org/pipermail/coreboot/2016-November/082541.html
BUG=none
BRANCH=none
TEST=none
Change-Id: I01226c6a9d0b20c70579b45754f898815abb803d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acbb70b810
Original-Change-Id: If1569618f8044925ff72dcf3543480b34d4f90d6
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/17636
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-on: https://chromium-review.googlesource.com/430677
That status isn't needed and making it non-static helps gcc 4.9.2 (or
any compiler that insists on "standard C" behaviour with global const
initializers)
BUG=none
BRANCH=none
TEST=none
Change-Id: I90c0d1ce22365b2276cf173f1e95d22ea50963a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c09e148b38
Original-Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/18266
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/435259
We rely on gnu make, so we can expect the jobserver to be around in
parallel builds, too. Avoids some make warnings and slightly speeds up
the build if those sub-makes are executed (eg for arm-trusted-firmware
and vboot).
BUG=none
BRANCH=none
TEST=none
Change-Id: I858f72696b7a3f3491ca950b4374735cbb363bb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78a5f22994
Original-Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/18263
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435403
Speed up the execution of this script from ~6 seconds to ~1 on my
system.
There are some changes to its output, but they're actually _more_
correct: so far, architectures without compiler support kept compiler
options for architectures that ran successfully earlier.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9944c810f432266e99a70a3c3cd9f1fc0fd5ef35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: be182ad380
Original-Change-Id: I0532ea2178fbedb114a75cfd5ba39301e534e742
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/18262
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435402
Reorder the items to minimize the differences.
BUG=none
BRANCH=none
TEST=none
Change-Id: I56a151e717f7ca3f8a3f9ca4106dfc73ea2be963
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7328cf948e
Original-Change-Id: I745ec70a990f997d87c2a0b6164ae127eb694ddf
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/17438
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435401
The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin'
implementation. It wasn't guarded though, so it was generating a build
warning for any other platform that generated an spd.bin file.
Sample warning that this fixes:
src/mainboard/gizmosphere/gizmo/Makefile.inc:42:
warning: overriding recipe for target 'build/spd.bin'
src/lib/Makefile.inc:298: warning: ignoring old recipe for target
'build/spd.bin'
BUG=none
BRANCH=none
TEST=none
Change-Id: I830ec92595c25005930599c02b5e1c71dc8e87bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e4bb3164a
Original-Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18261
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/435400
Apollolake boards should use DMIC-4ch configuration in Kernel side and
use CaptureChannelMap in userspace to distinguish boards with different
number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will
not be required and hence removed.
BUG=chrome-os-partner:60827
TEST=Verify internal mic capture
TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works
Change-Id: I7c66d5d7b22826c4141a3551624ef6c9b5163d73
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 545edca577
Original-Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8
Original-Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18252
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/435399
EC sets the logic level based on outstanding wake events. When GPIO_22
is configured as a level triggered interrupt, the events are not
cleared from the interrupt handler. Hence, we'd just be re-signalling
over and over causing an interrupt storm upon lid open. So, GPIO_22
needs to be configured as EDGE_SINGLE instead of LEVEL.
BUG=chrome-os-partner:62458
TEST=Lid close/open. check CPU usage using top. It should
not show 70% CPU usage.
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Change-Id: I5c6a65c35d217d4c62dcde004f78f024332cb3b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e5609124e
Original-Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a
Original-Reviewed-on: https://review.coreboot.org/18267
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/435398
For the boards that intend to use mock tpm and have recovery mrc cache
support enabled, provide mock functions to read and write mrc hash
space.
Reading MRC hash space returns TPM_SUCCESS as later checks take care of
comparing the hash value and retraining if hash comparison fails. Thus,
in case of mock tpm, device would always end up doing the memory
retraining in recovery mode.
BUG=chrome-os-partner:62413
BRANCH=None
TEST=Verified that eve builds with mock tpm selected.
Change-Id: Ib946ea2044a64286495a20a285ae5200702c24c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 775765eaf3
Original-Change-Id: I7817cda7821fadeea0e887cb9860804256dabfd9
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18248
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/435338
In some cases, we don't want the Chrome EC firmwares (both EC and PD)
built directly by the coreboot build system or included in images at
all. This is already supported with EC_EXTERNAL_FIRMWARE but it does
implement a binary (build and include) or (neither build nor include)
policy.
Some cases require the ability to separately control whether the EC
and PD firmwares should be built and included by the coreboot build
system, only included from externally-built images or not included
at all.
This introduces config changes implementing that behaviour, renaming
options to make it clear that they are specific to the Chrome EC.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:434278
Change-Id: Ie0b9e2063280a2b596a2d43afae855401319a959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ff24803a3
Original-Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/16033
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430678
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
This fixes the build for the generated code for boards with PS/2
keyboard, since commit 448e386309 updated the pc_keyboard_init()
function.
BUG=none
BRANCH=none
TEST=none
Change-Id: I02c1eaa937c3a3f3be0ca912091d132577f8e351
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bf53a9f4e
Original-Change-Id: I776b49b847985296eaca4af6d6e49ab5d6abbafe
Original-Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18242
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/434482
1. For ELAN, export reset GPIO as well as PowerResource
2. For WCOM, export PowerResource
BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Verified that touchscreen works on pyro with WCOM device on
power-on as well as after suspend/resume.
Change-Id: I5bc6c4d79d9606319c54ed3521b6ac2176ac51ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7a517ddc5
Original-Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18239
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434480
Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.
Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.
BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.
Change-Id: Ice3b1040d4cda0e5ac6d2a1f211dc8c8d78668cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 71d830fddc
Original-Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18238
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434479
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during
standby states S3/S0ix. This causes leakage of power. To reduce the
leakage, we have to pull these lines high during S3/S0ix. This is
done by programming the IOSSTATE to HIz. Also note that we are using
the internal pull ups to keep at SOC at 1.8V and the I2C lines are
not floating.
BUG=chrome-os-partner:62428,chrome-os-partner:61651
TEST=Enter S3/S0ix. Measure trackpad power. It should be less
than 4mW. Also I2c lines should be pulled high in S3/S0ix.
Change-Id: Icd735ff83676dd179eaa6c38bb2c25562ac3905a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f224e836c0
Original-Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733
Original-Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18251
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/434478
There will be more follow-up changes.
BUG=chrome-os-partner:62377
BRANCH=None
TEST=emerge-scarlet coreboot libpayload
Change-Id: I4804239483f8b35bc3703aa62c2a8fd642e0234a
Signed-off-by: philipchen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433039
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The SeaBIOS and coreboot log levels don't really align, so setting the
SeaBIOS log level to the same as coreboot's isn't really what we want.
- Update default log level to use the default SeaBIOS log level.
- Update the current help text to match the new defaults.
- Add help text for what is displayed at various levels.
- Get rid of separate type & prompt lines.
- Add comments for default seabios level & logging disabled
BUG=none
BRANCH=none
TEST=none
Change-Id: I4ce561f8b99aa000359aa86af23506274ffb4535
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8556db35e0
Original-Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18210
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-on: https://chromium-review.googlesource.com/433983
Currently coreboot runs the 'config' command if no .config file exists.
This isn't what anyone wants, and is particularly frustrating for tools
that automate the build, where the build just hangs waiting for input.
Instead, just show an error message and then exit the build.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8770f1f9be6990ca190a9fea78f340e0574e46bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20aa043b44
Original-Change-Id: If9e0c2c26f8273814518589a2f94c5b00fc4cefe
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18245
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433982
Intel Core 2 is not further specified since not all chipsets support
quad cores, which could confuse users.
BUG=none
BRANCH=none
TEST=none
Change-Id: I307abdaa1a3947a2fba21623aab6e40aadeff446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 017b56558f
Original-Change-Id: I86c0a41743fe784f432347fa639d3c26604e058e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18235
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433981
- Use dashes instead of underscores for consistency and to match other
coreboot targets
- Fix a couple of places where old target names were referenced
- Remove double 'help' target from .PHONEY target list
BUG=none
BRANCH=none
TEST=none
Change-Id: I7299b7aba9316f14dc963d3edaf313ce4c70cb11
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9ee70ce587
Original-Change-Id: I3b464ebf74653a8cc880e982316fd883757ec728
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18000
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433980
Kill running docker containers before trying to remove images or
containers.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6768e6f931e62ca9e079f4a13728581484d3b4f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af25fd78e8
Original-Change-Id: Id2de90edbe5d0dc6ecb906be7101ad9744dbd11e
Original-Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17999
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433979
- Fix TODO: restrict $1 to allowed values.
- Specifically exclude 'oem' board status directories.
- Exclude any directory that doesn't follow the date format to keep
the script from breaking again in the future if something it doesn't
recognize is pushed. Just ignore it for the wiki.
- Fix shellcheck warnings.
BUG=none
BRANCH=none
TEST=none
Change-Id: I55cee2d8a6fc1a605d77f6cc6d9eb9e2defa4872
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27f3ce6337
Original-Change-Id: I2864f09f5f1b1f5ec626d06e4849830400ef5814
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18225
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433884
Without this motherboards that requires a non zero timeout for ps2
keyboards on SeaBIOS don't build when CONFIG_UPDATE_IMAGE is set.
An alternative way to achieve this file would be to include a cbfsfile
instead of calling cbfstool. That way the file gets updated/added both
both image update and regular build. A difficulty of that approach is
that it needs to convert a decimal to a binary in little endian
representation, which is not a trivial thing to do in a Makefile.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4814675b2f006656d1bd6f418e38afadee6aeb80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7218a1e754
Original-Change-Id: Icafba8d3e279a2e70e607abba81e3dbebfb55e4b
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18231
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433883
If cmos is invalid, it doesn't make sense to read the value before
finding that out.
BUG=none
BRANCH=none
TEST=none
Change-Id: I99768c9fee002d965c8e98e36f5d385f9e9cd861
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e7a93fa65
Original-Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18236
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433882
The default macaddress in rt8168.c can be changed with a cbfsfile
called macaddress. This patch makes it possible to add such a file
using Kconfig at build time.
This also changes the name of the cbfsfile from "macaddress" to
"rt8168-macaddress" to avoid confusion.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib9c2286a9a382131cb1d1302202846b62c508f49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec74f45e72
Original-Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18088
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433881
Ubuntus default compiler flags for GCC [1][2] include `-Wformat
-Wformat-security`, causing errors similar like the one below.
```
CC romstage/northbridge/amd/amdht/ht_wrapper.o
src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify':
src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security]
printk(log_level, event_class_string_decodes[evtClass]);
^
[]
```
Fix that, by explicitly using a format string.
TEST=Built and booted on ASUS KGPE-D16.
[1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for
"fprintf, error: format not a string literal and no format arguments [-Werror=format-security"
[2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609.
Change-Id: Iff829bf83e1ead8537fbe5d7c5c6376bdd77f323
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f6776fa62c
Original-Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18208
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/433880
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I6715126e4aaa9e133fefc2eaa9c7457654e99af3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe8a01b01a
Original-Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18227
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/433878
me_cleaner is a tool to strip down Intel ME/TXE images by removing all
the non-fundamental code, while keeping the ME/TXE image valid and
suitable for booting the system. The remaining code (ROMP and BUP
modules) is the one responsible for the very basic initialization of
the ME/TXE subsystem and can't be removed.
This tool exploits the fact that:
* Each ME/TXE partition is signed individually and it is possible to
remove both the partition and the signature.
* The ME/TXE modules are not signed directly, instead they are hashed
and the list of their hashes is hashed again and signed: this
means that modifying a module doesn't invalidate the signature,
but only the hash of that single module.
* The modules hashes are checked only when the corresponding module
needs to be executed.
* The system can boot after the execution of the first module (BUP,
inside the FTPR partition), even if the subsequent stages fail.
Currently me_cleaner works on every Intel platform with Intel ME or
Intel TXE with the following limitations:
* Doesn't work when Intel Boot Guard is set in Verified Boot mode.
* Doesn't fully work on Nehalem yet.
* On Skylake and later generations, since the partitions' internal
structure has changed, me_cleaner leaves intact the FTPR
partition, removing all the the other partitions.
This tool has been tested on multiple platforms and architectures by
different users, and seems to be stable. The reports are available
here:
https://github.com/corna/me_cleaner/issues/3
A more in-depth description of me_cleaner is available here:
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
BUG=none
BRANCH=none
TEST=none
Change-Id: I4d697041a6d9df503d17a0e30fef4713120dddb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9bcc002f1e
Original-Change-Id: I9013799e9adea0dea0775b9afe718de5fc4ca748
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18203
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/432759
Make the code C89 compatible, which doesnt allow loop initial
declarations. Older compilers use C89 by default, so just declare the
variable outside.
BUG=none
BRANCH=none
TEST=none
Change-Id: If89c5f7ab563e8acde3150c57611a432d72509dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7385d14b1
Original-Change-Id: I3c5a8109e66f7a25687f4e4b2c72718d74276e04
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18196
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431984
Add support for Lenovo Thinkpad L520.
The files are generated by autoport,
and are successfully tested on the board.
L520 has got 4MiB flash chip, that contains a "slim" ME
with 1.2MiB only. The flash IC has to be desoldered, as
it won't be accessible in circuit. It is located on top
of the mainboard right under the touchpad.
Test-setup:
Extract the following blobs from vendor BIOS:
* Intel Flash Descriptor
* Intel Management Engine
* Intel VBios
The laptop has been externaly flashed. It was able to
turn on the display and load SeaBIOS.
Latest debian has been booted from harddisk.
Latest fedora has been booted from USB flash drive.
The following hardware has been tested and is working:
* Display using Option Rom
* PCIe wifi
* Ethernet
* Keyboard, trackpoint and touchpad
* Some Fn functions keys
* Volume Keys (except mic mute)
* Status LEDs
* Audio (headphone jack only)
* USB ports
* Native raminit dual channel (2 DDR3-1333 DIMMs tested)
* SATA cdrom
* SATA harddrive
Broken:
* Some Fn functions keys
* Microphone mute button
* Speakers (but headphone jack gives sound)
Untested:
* Expansion slot
* SD card slot
* Docking station
* Native gfx init
The EHCI debug port is the first one on the right side.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie7b248243339b52e6120c18ed217a740bc8992cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aae6e9cfe9
Original-Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18003
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431982
When .xcompile doesn't already exist, building libpayload fails because
the CC variable (et al) remain empty since .xcompile is only included
after the variables coming from there are evaluated.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie18787c4d871681de72e15ab6275a2f0003ed622
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b144a34c60
Original-Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18228
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/432758
It takes a long time for no gain: We don't need to update the
submodules, we don't need to fetch the revision, we don't need to find
the compilers, when all we want to do is to manipulate the .config file
or clean the build directory.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:432758
Change-Id: I2a2e65d1f5945885b43e32ecb8406f83f973c106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ffef882d8
Original-Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18182
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431983
This fixes building coreboot with -std=gnu11 on gcc 4.9.x
Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing
type.
BUG=none
BRANCH=none
TEST=none
Change-Id: I815127db725dd4bc3930e361d79d27a2a63eca80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06a629e4b1
Original-Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18220
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/431985
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1fb1184c5177437cc19824c14ec629440aaede80
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dcc0aa84fa
Original-Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18039
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431980
o Fix indentation and other whitespace issues,
o Use `const` where applicable,
o Avoid retyping the same constant literals,
o Actually read PCI revision from the device (instead of using the
lowest class byte).
BUG=none
BRANCH=none
TEST=none
Change-Id: I74c9feb687e8e8b42aeeb4ed7265547f289fd427
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d37fa8d84d
Original-Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/18185
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/431979
This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.
The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.
BUG=none
BRANCH=none
TEST=none
Change-Id: I28d51ae70b98abafbbfd68b38a59b00074bc89ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f1f0538cf
Original-Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18038
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/431978
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=chrome-os-partner:62206
BRANCH=none
TEST=plug in a charger to either port and see charge status updated to
indicate charging in the power_supply_info tool and the Chrome OS UI.
Change-Id: Ie4a2c145714636c43cf74168c119442cb0663635
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e949faec1
Original-Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18209
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/431977
`libhwbase` is a SPARK library that contains some basic support for i/o
access, debugging, timers. Just what I put around `libgfxinit`, to make
it build standalone.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifba116e967357ed971aecd8a1d1661a493c0ca81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e09f8acdad
Original-Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/16948
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/430675
If compression failed, just store the uncompressed data, which is what
cbfstool does as well.
BUG=chrome-os-partner:62235
BRANCH=none
TEST=none
Change-Id: I41f911169f376be3dab1335d93e1b3ff68ad7377
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b46c4ecaba
Original-Change-Id: I67f51982b332d6ec1bea7c9ba179024fc5344743
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18201
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430741
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia83222824b338692fbcfe67318da1ca7173f46a7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: eee4f6b224
Original-Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18022
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/431292
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
