Add a GNVS variable to store trackpad IRQ for google/parrot, so
that both SNB and IVB variants can be built with the same config
BUG=none
BRANCH=none
TEST=none
Change-Id: I66070de2cec7d70f80390557e03692d26a55ef68
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: aff9b30851
Original-Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20092
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539223
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Existing value was copied from librem13 v1 board, use value
obtained from AMI firmware.
TEST: Observe Windows boots correctly, function keys work
under both Windows and Linux.
BUG=none
BRANCH=none
TEST=none
Change-Id: I540b9124a88136993953026c845b8dc58b523682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 739ded5c18
Original-Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19945
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539222
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
BUG=none
BRANCH=none
TEST=none
Change-Id: I516cf6bb4b341743fea9110e300695d89aac92a2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5aaa8ce21c
Original-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19958
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539221
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- remove unused I2C, serialIO defs
- set PL2 override, VR mailbox cmd based on SKL-U ref board,
as values copied from google/chell are for SKL-Y
BUG=none
BRANCH=none
TEST=none
Change-Id: I2efdc5fb22c2d67fde95f7de37478b9bb1e333e6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2ae2742065
Original-Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19941
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539219
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Update devicetree USB config based on board spec.
Leave OC pins set to skip since the info is unavailable.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9c6f4ea63dcd09ec9aed4e8ae4ee53d32dcfaf3f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2fa66164d8
Original-Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19940
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539218
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Don't allow the user to set PCIe configspace base address.
Don't allow the user to set the DCACHE size and base.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic14c6b908edb31d371081c49b9388265eda21151
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9c27eda052
Original-Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20181
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539217
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I584088ba0b02411b8c59c6a5d84d1aa27bfd883f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 432ac615d0
Original-Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20180
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539216
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I6960f16a67860c0521be4eb621d028cfda7775ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 24c3fef31b
Original-Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20179
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539215
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
BUG=none
BRANCH=none
TEST=none
Change-Id: I0890bbb69183f2ec11c0c2fc3114ac29ee7321d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 48d6b76d53
Original-Change-Id: I254549057552be93611afa8ca52d22be220fe3dc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20178
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539214
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Does not need to changeable in menuconfig.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0bef7f608ed615d4c32dfbe475d424ad3680341c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3038b48de3
Original-Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20177
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539213
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
While building poppy board, build failed with following error message:
Writing new image to build/coreboot.pre.new
mv build/coreboot.pre.new build/coreboot.pre
util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null
This image does not contains a ME/TXE firmware NR = 0)
make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55:
add_intel_firmware] Error 1
Hence keeping CHECK_ME unset by default.
TEST=Succesfully built coreboot for Poppy & booted to OS.
Change-Id: Ie6de9fb169ae2225430651fe35109178194f20d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 95d6dd21c9
Original-Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19257
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539212
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This reverts commit f4835a85c0. It
completely ignores port coalescing and breaks enumeration in many
cases. The code reused to disable and hide the root ports was never
meant to be called that way.
The same effect of power saving can likely be achieved by clock
gating unused ports after enumeration without further, error-prone
function hiding.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibb8c6c2143324a3d366d838234ae0b2fe317fdaa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fc20926130
Original-Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/20216
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539211
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
A major regression was introduced with commit 6520e01a
(soc/intel/apollolake: Perform CPU MP Init before FSP-S Init)
where the APs execution context is taken away by FSP-S. It
appears that FSP-S is not honoring the SkipMpInit UPD because
it's been shown with some debug code that FSP-S is compeltely
hijacking the APs:
Chrome EC: Set WAKE mask to 0x00000000
Chrome EC: Set WAKE mask to 0x00000000
CBFS: 'VBOOT' located CBFS at [440000:524140)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 2e700 size 1a00
Running FSPS in 4 secs.. 315875 4315875
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
Running FSPS.. 4315875 4315875
ITSS IRQ Polarities Before:
ITSS IRQ Polarities Before:
IPC0: 0xffffeef8
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0x00ffffff
ITSS IRQ Polarities After:
IPC0: 0xffffeef8
IPC1: 0x4a07ffff
IPC2: 0x08000000
IPC3: 0x00a11000
This is essentially a revert of 6520e01a to fix the previous
behavior.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id678f145584418e76d0ffbb9884e58e6e55db9b6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ac3e48257e
Original-Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20215
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539210
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
TEST=Verified that board still boots to OS without any error.
Change-Id: I44c002e71e85017599a3f474941ced51c79e44d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 296c79c9be
Original-Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20143
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539209
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie64165f4b10fdae8ab64267f713a1feaaf1594c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dec6d4e8c7
Original-Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20142
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539208
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.
TEST=Verified that unused interface does not show up in ACPI tables.
Change-Id: I62356b4f834c95f4d5a6982c9e2d1d2131d68092
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b2f423578e
Original-Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20141
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539207
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If I2C device is disabled:
1. BAR for the device will be 0
2. There is no need to generate ACPI tables for the device
TEST=Verified that if an i2c device is disabled statically in
devicetree or dynamically in mainboard, then coreboot does not die
looking for missing resources.
Change-Id: I3617894691853f18b1ebb6f1fe26202d8d3ff502
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d629e433dd
Original-Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20140
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539205
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Initial support for undefined behavior sanitizer in ramstage. Enabling
this will add -fsanitize=undefined to the compiler command line and
link with ubsan.c in ramstage. Code with UB triggers a report with
error, file, and line number, then aborts.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifa0436eda099cceb1d238a1006d47c7d86793e10
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ab37e9a171
Original-Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20156
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539204
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fixes report found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= width of type is undefined. Add
ul suffix since it's safe for unsigned types.
BUG=none
BRANCH=none
TEST=none
Change-Id: I76262ee24dc89fac3d2b027ded72f1f32afaa580
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fce582fa1c
Original-Change-Id: I4b2365428e421085285006bc1ea8aea75890ff65
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20144
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539203
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that is not aligned to the size of access is undefined behavior.
Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other
write16()s in setup_ebda() to memcpy() for consistency.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic28f2b8d8b84a71b65ceb1a47015eef99a95319a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f0b0712023
Original-Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9
Original-Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-on: https://review.coreboot.org/20132
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539202
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
USB port status register can be used to decide if a particular port
was responsible for generating PME# resulting in device wake:
1. CSC bit is set and port is capable of waking on connect/disconnect
2. PLC bit is set and port is in resume state
BUG=b:37088992
TEST=Verified with wake on USB2.0 port 3, mosys shows:
19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3
Change-Id: I5e566b106bf896ca278a4ccf552d4d4be69736f0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ef08545bff
Original-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20122
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539201
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Also changes the arguments of some functions to const.
This reduces romstage size by a whopping 1009 bytes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7f0aba95153bf8aa822900880001d46049e966c1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6bf13012c1
Original-Change-Id: I054504412524b7be19d98081097843b61bc0c459
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20147
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539200
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa2ba1292cb6dc1a4a8098ee256044691f42daba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 01f9aa5e54
Original-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19789
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539199
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
If an MTRR solution exceeds the number of available MTRRs
don't attempt to commit the result. It will just GP fault
with the MSR write to an invalid MSR address.
BUG=none
BRANCH=none
TEST=none
Change-Id: I93cca7a563bc70aaa5d13163a37c89cd53605aac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d9762f70ac
Original-Change-Id: I5c4912d5244526544c299c3953bca1bf884b34d5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20163
Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539198
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
AMD_FAM10H code enables early cbmem by default.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ie52b4f096e2bd77ca6cd8fe12f3d3f9d0bf472be
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e1058c7c99
Original-Change-Id: Ifad007f6604bb612d544cf1387938a8fef1cceb4
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20148
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/539197
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Since this mainboard provides 3 COM ports on LPC, enable decoding of the
corresponding address range for COM 3.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae09fc6a1ef0457322c9d5c84fefcd06832bf248
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a00d84536b
Original-Change-Id: I15c0748fce67eef46401c314f441aa45f5e3c5fa
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20162
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/539196
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.
initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
src/ec/*/*/ec_lpc.c \
src/superio/*/*/superio.c \
src/superio/smsc/fdc37n972/fdc37n972.c \
src/superio/smsc/sio10n268/sio10n268.c \
src/superio/via/vt1211/vt1211.c
src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.
BUG=none
BRANCH=none
TEST=none
Change-Id: I40ce1f7f62ac7e9b82b974d314a8bc2335cf8cb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7daac91236
Original-Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Original-Signed-off-by: Samuel Holland <samuel@sholland.org>
Original-Reviewed-on: https://review.coreboot.org/20078
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Myles Watson <mylesgw@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539195
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
- use Siemens NC FPGA driver for backlight brightness and PWM control
- set Dsave time for board reset after falling edge of signal xdsave
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a51fce1d40d68dc2953a5f49213076f734121d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c21ba2cd3e
Original-Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20161
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539194
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The siemens/mc_apl1 mainboard needs more functionality provided by
Siemens NC FPGA. The additional functionality contains backlight
brightness/PWM control and Dsave time for board reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib9b98e0c5c9a350f84a0f520df3ec37a94760d8a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c4ff1de8bf
Original-Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20160
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539193
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The Siemens mc_apl1 mainboard needs new values from hwilib.
- add Dsave time for board reset
- add backlight brightness for panel setting
- add backlight PWM period
BUG=none
BRANCH=none
TEST=none
Change-Id: Idc3c86ccbd1d16f9b3ddd46a556a19dbe83f6dcf
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 59dd466414
Original-Change-Id: I3a48654ef57c7f8accaabe60e8aec144e4fe5466
Original-Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/20159
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/539192
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib535d95885606decf029206e615817a774e25029
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1d3661be0a
Original-Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://review.coreboot.org/20218
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/538580
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method and remove duplicated code in
acpi.c.
BUG=none
BRANCH=none
TEST=none
Change-Id: I27da90bcdeabd10454b16e366a47d3fb46bd57ad
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9aca643ccb
Original-Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19910
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/538579
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Add method gma_write_acpi_tables.
No need to update GNVS as it doesn't have ASLB.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib4b9afce32ada234f26322b8002c465bba74a596
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ee14ccca7a
Original-Change-Id: Ia138cfde2271a298c36b85e999ff69f0f211ba11
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19909
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/538578
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This driver reinvented MAINBOARD_DO_NATIVE_VGA_INIT in a very special
way: If it wasn't set, perform native gfx init in textmode, if it was
set, perform native gfx init in linear framebuffer mode. Test for
LINEAR_FRAMEBUFFER instead and make the native gfx init optional.
Also, make Kconfig reflect the actual behaviour.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ife5c5357bc5efef51d0def034b0fb3f3b4caaa45
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a1f842d158
Original-Change-Id: If20fd1f5b0f4127b426e8ff94acc61fcd4eb49af
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/20131
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/538577
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This was the single spot where VGA_BIOS_ID wasn't guarded by anything.
It resulted in the wrong default id if we didn't chose to add a VGA BIOS
at first but added one later (e.g. a board provided default guarded by
VGA_BIOS wasn't applied then, because the Via/CN700 value was already
set).
BUG=none
BRANCH=none
TEST=none
Change-Id: Idea0ab009cc745ce480031f144c8b66c9278198e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e8f6569ab3
Original-Change-Id: Ia16a5e6d194191d8da8c551d6eb3849bc65864a9
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/20101
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/538576
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icea02c61ca2846880b2a7a3f8b1b6c75b12972c4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 402e9c18dd
Original-Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19908
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/538575
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Use common init_igd_opregion method.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ieb90061fda4eeadb0c1131fc5682856833e8a337
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5c82026ca6
Original-Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19907
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/538574
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
BUG=none
BRANCH=none
TEST=none
Change-Id: I123e68c49e5329b5729cd593a0bb40f1156ec5f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d65ff22988
Original-Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20194
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/538573
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit 2e7f6cc introduced the 'no graphics init' option for
FSP 1.1 SoCs using a GOP driver to init the display, but selecting
that option while including a VBT breaks compilation for Braswell
and Skylake devices because the VBT and GOP driver are intertwined.
This patch decouples the VBT from the GOP driver execution,
allowing the 'no graphics init' option to compile (and work)
properly when CONFIG_ADD_VBT_DATA_FILE=y.
BUG=none
BRANCH=none
TEST=none
Change-Id: I25447b151e00c2505e7c6eff9411adbbadaa9848
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 660de34bbf
Original-Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/20210
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/538572
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icf0e46a75e0440c458f554de748d2e979dfffa30
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2e7f6ccafc
Original-Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19815
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533093
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7d9ee12b47caa8909bd204929adecfc7f78f027c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d4ebeaf475
Original-Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19814
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533052
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user
option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to
use the latter in a choice.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id68ef8d1fe1e00e03f8867d404c7b6b6e2ddd505
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 26ce9af9a0
Original-Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19813
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/533051
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Make the "Display" menu a submenu of "Devices", place it below the
graphics options and reorder options by their dependencies.
BUG=none
BRANCH=none
TEST=none
Change-Id: I20f098649aebf71de278ff233df59081896a21a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a2cf686396
Original-Change-Id: I9de3d8f76ae10b0a77678ce2d71f840fac32379c
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19806
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/533050
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Remove the weak function stub fill_lb_framebuffer() and guard with the
new `CONFIG_LINEAR_FRAMEBUFFER` instead.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibd4095700b0e89eb9c933df30af00e7acb43bb7f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ce768f3baf
Original-Change-Id: Ia9e477c2d501b249a632968b5636ac803323895a
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19807
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/533049
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
BUG=none
BRANCH=none
TEST=none
Change-Id: I095dd4f36d853de51387895bace494840aaca3c1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6d8266b91d
Original-Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19804
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533048
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
BUG=none
BRANCH=none
TEST=none
Change-Id: If1746137edf2c976786e5b1a73c079d7e6c0f6d6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7971582ec4
Original-Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/19800
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533047
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I388e134017ee441cbd67b9a66fdbc07d992c9650
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ce642f08b9
Original-Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19791
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533046
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig
guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be
selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro-
vide their own fill_lb_framebuffer() implementation.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5c147f429580ad3c43ff255c1a059196fc8cf1f5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 3db7653aab
Original-Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19764
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/533045
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
